Seongho Moon

Realistic adsorption geometries and binding affinities of metal nanoparticles onto the surface of carbon nanotubes

Adsorption geometries and binding affinities of metal nanoparticles onto carbon nanotubes (CNTs) are investigated through density-functional-theory calculations. Clusters of 13 metal atoms are used as models for metal nanoparticles. Palladium, platinum, and titanium particles strongly chemisorb to the CNT surface. Unlike the cases of atomic adsorptions the aluminum particle has the weakest binding affinity with the CNT. Aluminum or gold nanoparticles accumulated on the CNT develop the triangular bonding network of the metal surfaces in which the metal-carbon bond is not favored. This suggests that the CNT-Al interface is likely to have many voids and thus susceptible to oxidation damages.

Selective growth of carbon nanotube for via interconnects by oxidation and selective reduction of catalyst

We propose a selective growth approach of carbon nanotubes (CNTs) to prevent interface rupture in CNT via interconnects. Oxidation of the Ni catalyst layer is carried out before via hole patterning and the open hole area of the Ni layer is reduced by annealing in H2 ambient after via hole patterning. It is found that the present scheme provides robust selective growth of CNTs in the via hole and effectively prohibits the interface rupture due to the diffusion of carbon source into the Ni catalyst layer buried under the insulator.

The new test pattern selection method for OPC model calibration, based on the process of clustering in a hybrid space

Model-based Optical Proximity Correction (OPC) is widely used in advanced lithography processes. The OPC model contains an empirical part, which is calibrated by fitting the model with data from test patterns. Therefore, the success of the OPC model strongly relies on a test pattern sampling method. This paper presents a new automatic sampling method for OPC model calibration, using centroid-based clustering in a hybrid space: the direct sum of geometrical sensitivity space and image parameter space. This approach is applied to an example system in order to investigate the minimum size of a sampling set, so that the resulting calibrated model has the error comparable to that of the model built with a larger sampling set. The proposed sampling algorithm is verified for the case of a contact layer of the most recent logic device. Particularly, test patterns with both 1D and 2D geometries are automatically sampled from the layer and then measured at the wafer level. The subsequent model built using this set of test patterns provides high prediction accuracy.

Physical simulation for verification and OPC on full chip level

In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.

Computational Process Optimization of Array Edges

DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features. Resolution Enhancement Techniques are used to optimize the periodic pattern process performance. This is often realized with aggressively coherent illumination sources supporting the periodic pattern pitch only and making an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from periodic patterns to non periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Non functional dummy structures are very effective to support the outermost edge but are very expensive, so their reduction or avoidance directly increases chip space efficiency. This paper focuses on how to optimize the DRAM array edge automatically in contrast to manual optimization approaches that were used effectively but at high cost. We will show how to squeeze out the masks degrees of freedom to stay within tight pattern tolerances. In that way we minimize process variations and the need of costly non-functional dummy structures. To obtain the best possible results the optimization has to account for complex boundary conditions: correct resist effect prediction, mask manufacturability constraints, low dose, low MEEF, conservation of symmetries and SRAF printing, simultaneous optimization of main features and SRAFs. By incorporating these complex boundary conditions during optimization we aim to provide first time right layouts without the need for any post processing.

Optical performance comparison between negative tone development and positive tone development

A negative tone development (NTD) process has been considered as apromising candidate for the smaller contact solution due to the remarkable image quality over a positive tone develop (PTD) process. However, it has not been investigated why NTD has higher optical performance than PTD yet. In this paper, image log slope (ILS) and mask error enhancement factor (MEEF) of binary and phase shift masks (PSM) are investigated with considering mask bias, target critical dimension (CD) and pattern pitch. It is found that the irradiance slope is steep and wafer CD variation from mask CD variation is small when the target CD is relatively smaller than pattern pitch. Mathematical model is derived to analyze image quality of binary mask and PSM.Three-dimensional mask effect is also considered with rigorous simulation.

Fine calibration of physical resist models: the importance of Jones pupil, laser bandwidth, mask error and CD metrology for accurate modeling at advanced lithographic nodes

In this paper, we discuss the accuracy of resist model calibration under various aspects. The study is done based on an extensive OPC dataset including hundreds of CD values obtained with immersion lithography for the sub-30 nm node. We address imaging aspects such as the role of Jones matrices, laser bandwidth and mask bias. Besides we focus on the investigation on metrology effects arising from SEM charging and uncertainty between SEM image and feature topography. For theses individual contributions we perform a series of resist model calibrations to determine their importance in terms of relative RMSE (Root Mean Square Error) and it is found that for the sub-30 nm node they all are not negligible for accurate resist model calibration.

New method to determine process window considering pattern failure

In this paper, new metric, acid concentration distribution image log slope (AILS) is suggested to predict pattern failure in photo lithography. By introducing AILS, pattern fidelity can be determined as numbers. With evaluating at the top 10% and bottom 10% of photo resist, various kinds of pattern failures are categorized and they can be predicted to be failed or not. The simulation results are compared with wafer experiment results and shows great prediction accuracy. In order to evaluate hot spot regarding pattern failure in all possible pitch and duty ratio, in-house image quality analysis tool is used and compared with wafer experimental results. Minimum normalized AILS (NAILS) to cause pattern bridge is larger than that to cause lift off. Both pattern failures are dependent of AILS and CD but the effect of CD on pattern failure is stronger than AILSs