Seongjong Kim

Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique

This paper presents a design approach for upgrading the resiliency of ultra-low-voltage (ULV) microprocessors through a voltage-scalable and low-overhead in-situ error detection and correction (EDAC) technique. Particular efforts are made to overcome the poor voltage scalability and area/energy/throughput overhead of the existing EDAC techniques when applied to ULV designs. The 16 bit microprocessor employing the proposed EDAC and dynamic voltage scaling schemes is demonstrated in a 65 nm. The microprocessor can automatically modulate VDD based on timing error flags across static/slow variations and in-situ detect and correct the timing errors from fast dynamic variations, virtually eliminating timing and voltage margins. At a typical process/voltage/temperature corner, the proposed design improves the minimum energy consumption by 42% with 140 mV additional voltage scaling, as compared to the baseline design. At the same throughput (80 MHz), the proposed design consumes 38% less energy than the baseline operating at its minimum energy point. At the same energy consumption, the proposed design achieves 2.3 × higher throughput than the baseline design. The area overhead of the proposed design is 8.3%.

Razor-lite: A light-weight register for error detection by observing virtual supply rails

This paper presents Razor-Lite, which is a low-overhead register for use in error detection and correction (EDAC) systems. These systems are able to eliminate timing margins by using specialized registers to detect setup time violations. However, these EDAC registers incur significant area and energy overheads, which mitigates some the system benefits. Razor-Lite is a new EDAC register that addresses this issue by adding only 8 additional transistors to a conventional flip-flop design. The Razor-Lite flip-flop achieves low overhead via a charge-sharing technique that attaches to a standard flip-flop without modifying its design. Side-channels connected to the floating nodes generate error flags through simple logic gates totaling 8 transistors, enabling register energy/area overheads of 2.7%/33% over a conventional DFF, while also not incurring extra clock or datapath loading or delay. Razor-Lite is demonstrated in a 7-stage Alpha architecture processor in a 45nm SOI CMOS technology with a measured energy improvement of 83% while incurring a 4.4% core area overhead compared to a baseline design.

Compact and Supply-Voltage-Scalable Temperature Sensors for Dense On-Chip Thermal Monitoring

This paper presents compact and voltage-scalable temperature sensor circuits for implementing dynamic thermal management (DTM) in high-performance microprocessors and Systems-on-Chips (SoC). The proposed sensor front ends require only 6 to 8 NMOS transistors, resulting in more than one order of magnitude smaller area than the previous state of the art. The sensor supply voltage can be scaled down to 0.6 V, so it can be integrated with digital circuits employing a dynamic-voltage-scaling technique without additional power distribution and regulation. Sensor front ends with three different sizes (115, 279, and 400 μm2) and their back ends have been prototyped in a 65 nm CMOS technology. The measurement results of the 279 μm2 front end at 0.6 V show a worst-case error of 7.0° C across 64 instances 0° C to 100° C after a low-cost one-temperature-point calibration. With the same conditions, the measurements of the 400 μm2 front end show a worst-case error of 5.4° C across 64 instances. The compact sensor designs make it possible to integrate an order of magnitude more sensors on a chip with little additional overhead and thereby enable very dense thermal monitoring in digital VLSI systems.

R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS

This paper presents a design approach for upgrading the resiliency of ultra-low-voltage (ULV) microprocessors through a voltage-scalable and low-overhead in-situ error detection and correction (EDAC) technique. Particular efforts are made to overcome the poor voltage scalability and area/energy/throughput overhead of the existing EDAC techniques when applied to ULV designs. The 0.4 V, 16 b microprocessor employing the proposed EDAC and dynamic frequency scaling schemes is demonstrated in 65 nm. The microprocessor can (1) automatically modulate fCLK based on error flags across static/slow variations and (2) in-situ detect and correct the errors from fast dynamic variations, virtually eliminating timing margins. At a typical process/voltage/temperature (PVT) corner, the proposed design achieves 4.9× throughput and 59% energy efficiency improvement at only 9.5% area overhead over the baseline design under the worst-case timing margin.

Analysis and optimization of in-situ error detection techniques in ultra-low-voltage pipeline

In-situ error-detection and correction techniques have a strong potential to eliminate the worst-case margins in ultra-low-voltage (ULV) pipelines while achieving high variation tolerance. Adding the capability of error detection, however, can incur large hardware overhead, especially in ULV due to the larger variability. In this paper, we analyze the hardware overhead of error-detection techniques and propose a technique called sparse insertion of error-detecting registers. The proposed technique, applied on benchmark 3-stage pipeline operating at 0.35V, can reduce the error-detecting register count by 1.3-4.3×, total area by 15-40% and timing violation rate by 19-37×, compared to the conventional techniques.

A 450mV timing-margin-free waveform sorter based on body swapping error correction

We propose an error detection and correction technique based on local body swapping for eliminating the worst-case margin in near/sub-VTH non-instruction parallel architectures. We apply the proposed technique on an unsupervised waveform sorter for brain computer interface microsystems, improving energy-efficiency by 49.3% and throughput by 35.6% over the baseline that is margined for the worst-case variation. The area overhead is 4.1%.

Reconfigurable regenerator-based interconnect design for ultra-dynamic-voltage-scaling systems

Ultra-dynamic-voltage-scaling (UDVS) is a compelling technique to use nominal supply voltage (VDD) for providing peak performance while achieving high energy efficiency by opportunistically using near/sub-threshold VDDs under average and low workload. One of the challenges in developing UDVS systems is that circuit fabrics optimized for a specific VDD can exhibit largely sub-optimal performance and energy efficiency at other VDDs. One critical example is the repeater-based interconnect design where the optimal interval of repeater insertion varies with VDD. In this paper, we propose a reconfigurable interconnect design based on an optimized regenerator to improve performance and energy efficiency across a wide range of VDDs.

Near-Vt adaptive microprocessor and power-management-unit system based on direct error regulation

We present a co-design approach of a near-threshold voltage adaptive microprocessor and power-management unit (PMU). It consists of (i) a microprocessor with in-situ error detection and correction; (ii) an integrated 63-ratio switched-capacitor DC-DC converter; and (iii) an error-based controller which regulates the timing error rate of microprocessor directly instead of indirectly through regulating PMU output voltage. The measurement of the prototyped chips shows a significant improvement in system-level efficiency that considers both power conversion and consumption.

Compact and voltage-scalable sensor for accurate thermal sensing in dynamic thermal management

Todays microprocessors and Systems-on-Chip are thermally limited. Many, therefore, employ dynamic thermal management (DTM) to maximize performance under a reliability constraint. Accurate thermal monitoring is critical as temperature underestimation can hurt reliability by excessively aging devices and overestimation can hurt performance by unnecessarily throttling computing components. Placing temperature sensors close to potential hotspots can help accuracy, but it is non-trivial as hotspots often form inside digital blocks consisting of densely placed digital cells. Large sensors can disrupt cell placement thereby increasing wire lengths and circuit delays. Furthermore, the sensor needs to operate from the same digital power grid as the circuit, one that can be scaled down to near-threshold regime via dynamic voltage scaling. Absent this ability, a separate power grid and dedicated supply voltage for the sensors further increases area overhead. In this paper, we present a sensor circuit that is compact and deeply voltage-scalable and can be embedded among digital cells with little disruption. Simulation results show that it achieves a comparable accuracy to other compact sensor circuits for DTM.

1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision

This paper presents algorithm/hardware co-design for real-time unsupervised spike sorting hardware for reducing power and improving sorting accuracy. We devise an algorithm based on Bayesian decision, which enables high accuracy while using noisy and simple time-domain features. Those simple features significantly reduce computation complexity, memory requirement, and thus the required number of cycles per sorting. The latter, coupled with the sparsity of spikes in time, makes the hardware idle for most of time, and thus we employ aggressive power gating and balloon latches to sleep most of the circuits and wake them up only when a spike is detected for maximal power savings. The hardware prototyped in a 65nm achieves higher accuracy at lower power than the existing arts.