Tae-Kyung Oh

RTS-like fluctuation in Gate Induced Drain Leakage current of Saddle-Fin type DRAM cell transistor

RTS (random telegraph signal)-like fluctuation in Gate Induced Drain Leakage (GIDL) current of Saddle-Fin (S-Fin) type DRAM cell transistor was investigated for the first time. Furthermore, two types of fluctuation which have apparently different τhigh (average time duration of high leakage state) to τlow (average time duration of low leakage state) ratio were investigated, and it was found that the energy difference between bistable levels is similar to that of the junction leakage.

Limitation of WSix/WN Diffusion Barrier for Tungsten Dual Polymetal Gate Memory Devices

We compared WSix/WN and Ti/WN diffusion barriers for tungsten dual polymetal gate (W-DPG) application, in terms of device performance and gate oxide reliability. WSix/WN diffusion barrier shows degradation of gate oxide, which is found to be due to the B-N dielectric formation and subsequent breakdown of diffusion barrier. Relatively, Ti/WN diffusion barrier shows excellent device performance in terms of R/O delay and gate oxide reliability

Low resistive tungsten dual polymetal gate process for high speed and high density memory devices

We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B2H6-based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.

Design and fabrication of X-band AlGaAs/GaAs power HBTs

We performed systematical thermal design and fabricated X-band 0.5 W class power HBTs. Based on the thermal design, we adopted an HBT with emitter-to-emitter spacing of 30 /spl mu/m as a standard device. The collector-emitter breakdown voltage is 16 V indicating that 8 V operation is possible. f/sub t/, f/sub max/ and output power of the HBT at 10 GHz are 67, 58 GHz and 0.58 W, respectively. Various kinds of HBTs with different structures have been studied for reducing the thermal effects and we will present the dominant effect on thermal problems and the measurement data for thermal design guide.

Effect of La2O3 Capping Layer Thickness on Hot-Carrier Degradation of n-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with High-k/Metal Gate Stacks

The effect of La2O3 capping layer thickness on the hot-carrier degradation of n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with high-k/metal gate stacks is investigated. The hot-carrier degradation is monitored by measuring the threshold voltage Vth, transconductance gm, and subthreshold slope SS. As the thickness of the La2O3 layer increases, Vth degradation is enhanced regardless of whether the La2O3 layer is deposited above or below the HfSiO layer. The generation of interface traps induced by hot-carrier stress is intensified with an increase in the bottom capping layer thickness. On the other hand, the generation of oxide traps induced by hot-carrier stress is intensified with an increase in the top capping layer thickness.

Study on the Sub-Threshold Margin Characteristics of the Extremely Scaled 3-D DRAM Cell Transistors

This paper proposes an equivalent circuit model of 3-D DRAM cell transistors with recess gate and saddle fin structure for the first time. The model effectively characterize the sub-threshold and off margin behavior of the scaled DRAM cell transistor by considering the parasitic sub-channel and vertical transistor components into account. TCAD simulation and experimental data have confirmed the accuracy of the model. With the analysis made, we suggest a set of improvement method for the off margin characteristics engineering. These methods are believed to lead the continuous DRAM scaling, down to sub-10nm technology node.

Effect of Gate Oxide Thickness Uniformity on the Characteristics of Three-dimensional Transistors

Heung-Jae Cho, Tae-Yoon Kim, Yong Soo Kim, Se-Aug Jang, Seung Ryong Lee, Kwan-Yong Lim, Min Gyu Sung, Jong-Hyeop Kim, Sang-Won Oh, Tae-Woo Jung, Tae-Kyung Oh, Yun-Taek Hwang, Young-Hoon Kim, Hong-Seon Yang, and Jin-Woong Kim R&D Division, Hynix Semiconductor Inc., Ichon P.O. Box 1010, Ichon-si, Kyoungki-do 467-701, Korea (Phone: +82-31-630-4466, Fax: +82-31-630-4545, e-mail: heungjae.cho@hynix.com)