Sergey Sofer

Inter-symbol interference (ISI) in on-die transmission lines

The waveforms of a signal transmitted through single-ended on-die transmission lines, implemented by standard metal layers of a CMOS 45 nm technology node, have been experimentally studied. The influence of the active loss level of the lines, as well as of the impedance mismatch between the transmission line and its driver upon the signal distortion, and particularly upon the inter-symbol interference, is discussed.

Aggravated Electromigration of Copper Interconnection Lines in ULSI Devices Due to Crosstalk Noise

In this paper, the impact of crosstalk noise between two adjacent interconnection lines, namely, the aggressor and a victim line, upon electromigration (EM) and Joule-heating failure mechanisms in ULSI microchips has been studied. It was shown that the crosstalk noise leads to distortions of signal waveforms at the far end of the victim line, i.e., the signals supplied to the input of a far-end CMOS inverter. As a result, the shape of the inverters currents, flowing through the next-stage line (i.e., the line that loads this inverter), is modified in such a way that both EM and Joule heating of the next-stage line are aggravated. The studies reveal that the most deleterious scenario of the crosstalk noise is when the victim and aggressor are switching in opposite directions and the aggressor begins to switch around the trip point of the victims far-end CMOS inverter (i.e., when both nMOSFET and pMOSFET are open and in a triode mode). Thereby, the crosstalk noise is not only a signal integrity issue as it has been traditionally regarded but also a serious reliability concern that should be taken into account in corresponding reliability models.

Fast and noise-aware power-up for on-die power gated domains

On-die PSO is used for leakage power reduction. The power-up process at PSO exit (gated supply voltage recovery) is usually designed to be relatively slow process. This is done in order to keep quiet continuous power supply of always powered-on devices. We propose a way of acceleration the power-up, while holding the continuous power supply at acceptable level of noise. This is achieved by monitoring the IR droop level of the continuous power supply. It allows significant reduction of the power-up time with no functionality impact. The theoretical background, the arrangement schematics and the simulation results are presented.

Investigation of on-chip PLL irregularities under stress conditions - case study

In modern high performance VLSI design, on-chip phase locked loop (PLL) performance degradation due to intensive core switching activities is becoming an influential factor. Under certain borderline conditions, the PLL may become unstable. The analysis herein describes PLL irregularities under marginal mode, frequency and voltage conditions combined with intensive core operations. After lengthy analysis that included step-by-step elimination of all noise sources, the cause of instability was explained by coupling between a voltage spike on core power supply line and the internal control signal of the voltage controlled oscillator of the PLL through the chip substrate. The solution to the problem was suggested by changing the PLL dynamic characteristics. Through this investigation we studied the noise crosstalk issue in mixed mode (analog and digital) systems and also the PLL dynamics under stress conditions, which demonstrates the complexity of PLL analysis in a system-on-chip environment.

Automatic system for VLSI on-chip clock synthesizers characterization

Analyzing the ability of clock generation circuits to provide a high quality chip clock for synchronous systems is very critical. This is important in order to ensure stable functioning of such systems at the highest frequencies, in addition to ensuring reliable communications between core, on-chip peripherals, external peripherals and memory. We propose a clock synthesizer characterization system, which performs measurements automatically, according to the clock synthesizers mode, frequency, power supply voltage and ambient temperature. The system is intended to work in both quiet and noisy environments. The accuracy of the measurements, together with the systems high flexibility and speed, allows on-the-spot characterizations, which in turn results in a detailed, statistically reliable picture of the clock signals quality. Practical experience has shown that this system is effective, not only for clock synthesizer characterization, but for failure analysis as well.

Synchronous duty cycle correction circuit

A duty cycle correction (DCC) circuit with deterministic clock insertion delay is presented. To neutralize the ambiguity of the DCC circuit insertion delay induced by the wide range of input clock duty cycle, a signal differentiating circuit at the input of the circuit is used which narrows the input duty cycle range to the circuit core. We achieved deterministic delay between rising edges of the input and output clock signals, defined as four inverting stages only, that allowed successful integration of the circuit into the custom clock tree structure in a system-on-chip, keeping the same clock delay for all its branches: having corrected and not corrected duty cycle.

Inductance Considerations of on-Chip Interconnections for Best Electrostatic Discharge Protection Performance

The inductance of the on-die interconnection lines may cause voltage resonant effects under electrostatic discharge (ESD) stress. The phase difference of the resonating oscillations along different ESD current flow paths creates a significant local momentary voltage. Information on this inductance enables designers to take into consideration these voltage resonant effects in ESD protection design

High Coverage Power Integrity Verification in PSO Domains Employing Distributed PSO Switches

Proposed a way to increase the coverage of power distribution network verification, especially applicable for designs, employing distributed power gating switches. It includes defining of amount of CMOS devices (in the same cluster) simultaneously toggling at the same place and following voltage droop analysis of whether amount of devices, belonging to the same cluster, toggle above the predefined threshold, all over the functional pattern(s). Additionally, we define clear guidelines to the implementation tools how constantly toggling CMOS devices like clock buffers, are expected to be placed in order to avoid PDN failures. Some examples of the proposed approach are provided.

Improved Reliability and Functionality of Clock Networks in ULSI Devices Due to Lossy Transmission Line Modeling Method

In this paper, the ways to improve the functionality and reliability of Digital Signal Processors, used to support optical networks, have been studied. Specifically, supported on our finding from previous experimental studies that on-die global interconnects should be described by a distributed RLC model, we propose to model shielded lines, carrying the most critical signals, by a Lossy Transmission Line (LTRA) model. The proposed method obviates the need for tedious simulations, which also due to many inevitably required oversimplifications have a low correlation with a real circuit behavior. The SPICE simulated signal waveforms obtained at the far-end of shielded lines correlate well with experimentally measured waveforms within a typical 45 nm CMOS technology ULSI chip. Based on both, simulations and experimental measurements, we have construed criteria whereby we modified the CMOS driver strength selection guideline to conform to the distributed nature of on-die interconnection lines. The performed simulations on a multi-level clock H-tree structure from a high-performance core block indicate that the new approach considerably improves MOSFETs reliability and power dissipation.

Novel method for debug of electrostatic discharge protection in VLSI circuits

A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure