Valery Neiman

Fast and noise-aware power-up for on-die power gated domains

On-die PSO is used for leakage power reduction. The power-up process at PSO exit (gated supply voltage recovery) is usually designed to be relatively slow process. This is done in order to keep quiet continuous power supply of always powered-on devices. We propose a way of acceleration the power-up, while holding the continuous power supply at acceptable level of noise. This is achieved by monitoring the IR droop level of the continuous power supply. It allows significant reduction of the power-up time with no functionality impact. The theoretical background, the arrangement schematics and the simulation results are presented.

Synchronous duty cycle correction circuit

A duty cycle correction (DCC) circuit with deterministic clock insertion delay is presented. To neutralize the ambiguity of the DCC circuit insertion delay induced by the wide range of input clock duty cycle, a signal differentiating circuit at the input of the circuit is used which narrows the input duty cycle range to the circuit core. We achieved deterministic delay between rising edges of the input and output clock signals, defined as four inverting stages only, that allowed successful integration of the circuit into the custom clock tree structure in a system-on-chip, keeping the same clock delay for all its branches: having corrected and not corrected duty cycle.

High Coverage Power Integrity Verification in PSO Domains Employing Distributed PSO Switches

Proposed a way to increase the coverage of power distribution network verification, especially applicable for designs, employing distributed power gating switches. It includes defining of amount of CMOS devices (in the same cluster) simultaneously toggling at the same place and following voltage droop analysis of whether amount of devices, belonging to the same cluster, toggle above the predefined threshold, all over the functional pattern(s). Additionally, we define clear guidelines to the implementation tools how constantly toggling CMOS devices like clock buffers, are expected to be placed in order to avoid PDN failures. Some examples of the proposed approach are provided.