Eric E. Fabris

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Abstract Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the gm/ID characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the gm/ID characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.

Development of a WirelessHART compatible field device

The use of wireless industrial field devices (sensors and actuators) is gradually increasing. The easy installation and repositioning of these devices are the greatest motivators of this tendency. On the other hand, wave propagation phenomena, radio frequency coexistence and energy consumption are inherent difficulties that must be taken into account. The applied wireless communication protocol must cope with these difficulties and avoid or minimize them. In this paper, the WirelessHART protocol is introduced as well as the development of a compatible field device. A data logger software and firmware are developed to test the system. The results are presented at the end and can be used to help in the development of new devices.

An analog signal interface with constant performance for SoCs

This paper describes a new architecture for programmable analog interface circuits. One of the main consequences of analog programmability is the performance penalty introduced by this feature. The proposed new architecture attenuates the programmability penalty and, even more important, it provides constant performance over a wide range of input signal band. Using a mixer inside the proposed architecture, we propose an analog programmable interface that can process signals from DC to high frequencies with constant performance, overcoming the need to change the architecture as a function of the target domain application. This paper presents the mathematical framework and experimental results showing the proposed architecture applied to linear filter design over a large frequency range.

Self-biased CMOS Current Reference based on the ZTC Operation Condition

A self-biased current reference based on the MOSFET Zero Temperature Coefficient (ZTC) condition is presented. It can be implemented in any CMOS process and it provides a simple alternative to design a reference current suitable for low TC biasing. This topology was designed in a 0.18 μm process to generate 5 μA under a supply voltage from 1.4V to 1.8 V, spending a silicon area around 0.010mm2. From circuit simulations, the current reference is estimated to have a temperature coefficient (TCeff ) of 15 ppm/°C from -40 to +85 °C and a fabrication sensitivity of σ/μ = 4.5%, including average process and local mismatch variability. The power supply sensitivity resulted around 1%V for this new reference.

A Low-Voltage Current Reference with High Immunity to EMI

An electromagnetic interference (EMI) source can significantly degrade the performance of a current reference since its finite Power Supply Rejection Ratio (PSRR) of the later. For that reason A modified current reference with high immunity to EMI and a new current mirror structure insensitive to induced EMI are proposed based on the classic boot-strapped current and compared to other current reference structures. Simulations results using XFAB 0.18 μm CMOS process demonstrate the high immunity to EMI of the proposed current reference. Improvements in the PSRR of 48dB and 32dB in comparison to the classical version and other implementations respectively.

A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference using zero- V T active loads

A low-voltage high-PSRR CMOS voltage reference operating with picowatt power consumption is presented. The voltage reference is generated from the threshold voltage (VT) difference of two transistors biased in weak inversion. The VT difference is achieved through its dependence with the transistor dimensions. The high-PSRR is obtained using zero-VT transistors as active loads. The final circuit was designed in a 130 nm CMOS process and occupies around 0.0007 mm2 of silicon area while consuming just 18.5 pW at 27°C. Post-layout simulations present a 62 mV reference voltage with a temperature coefficient of 15 ppm/°C, for a temperature range from -25 to 125 °C and a Power Supply Rejection Ratio (PSRR) of -68.7 dB at 0.3 V of supply voltage.

Resistorless switched-capacitor current reference based on the MOSFET ZTC condition

The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and voltage references. This condition is usually analyzed using the strong inversion quadratic MOSFET model. In this work we use a different approach, based on a continuous MOSFET model that can predict its behavior from weak to strong inversion. Based on this analysis, we verify that the ZTC point occurs from moderate to strong inversion for any CMOS process, since this point must occur for gate-source voltages larger than one threshold voltage. Also, a resistorless switched capacitor current reference based on the ZTC condition (ZSCCR), presenting low temperature coefficient (TC), is presented. The ZSCCR is designed in a 180 nm process, resulting a reference current of 5.88 μA under a supply voltage of 1.8 V, and occuping a silicon area around 0.010mm2. Results from circuit simulation show an effective temperature coefficient (TCeff ) of 60 ppm/°C from -45 to +85 °C and a power consumption of 63 μW.

Wireless portable sensor for athletic monitoring

Physical activities are an essential characteristic for the maintenance of health and fitness of an individual. The advances in microelectronics allowed the development of miniature data acquisition devices that can be used for constant monitoring of human health. This paper presents a study and development of a portable device, using appropriate methods for the acquisition of vital signs and physical character analysis. The development of a non-invasive method where the vital signs are acquired and wirelessly transmitted is presented. The obtained results are reported, presenting the feasibility of the proposed methods and the possible improvements that can be done. The results suggested that the employed techniques are adequate and the developed prototype can be used by physical educators and ordinary people to collect vital signs during physical exercises.

CMOS RF class-E power amplifier with power control

This paper proposes a 2.2 GHz CMOS Power Amplifier (PA) useful to S-Band applications with an effective 3-bit output power control for efficiency improvement. It uses an input transformer to reduce ground bounce effects and operates around 1 W of output power. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for efficiency improvement, composed by four parallel branches where the state (on or off) of 3 branches is separately activated by a 3-bit input. The class-E power stage uses a cascode topology to minimize the voltage stress over the power transistors, allowing higher supply voltages. The PA was designed in a 130 nm RF process and post-layout simulations resulted a peak output power of 28.5 dBm with a maximum power added efficiency (PAE) around 47% under 3.3 V of supply voltage. The 3-bit control allows a total output power dynamic range adjustment of 12.4 dB, divided in 8 steps, with the PAE changing from 13.4% to 47.3%.

Analog IC modules design using trapezoidal association of MOS transistors in 0.35 /spl mu/m technology

This works addresses how analog modules can be designed in a pre-diffused array of digital - i.e. minimum length - transistors. The mapping of each original single transistor of the circuit into an equivalent trapezoidal association of digital transistors (TAT) is analyzed. Three methodologies for the calculation of the equivalent TAT are presented: a linear resistor, a current model and a small-signal equivalent array approximation. These methods are applied to two IC modules designed with TAT associations in 0.35 /spl mu/m technology to show the effect of the single-to-TAT conversions and to compare the conventional and the TAT design: a two-stage Miller operational amplifier and a track-and-latch switched analog comparator. The results are compared to the performance of the single-transistor designs, showing that minimum-length digital transistors can be properly arranged to obtain reasonable specifications for middle performance analog circuits. The advantages of the digital array are the reduced prototype time. The layout design of the TAT associations and of the full modules were done with LIT, an interactive layout tool.