Hamilton Klimach

A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling Design

Component tolerances and mismatches due to process variations severely degrade the performance of bandgap reference (BGR) circuits. In this paper, the authors describe the design of a BGR considering the Pelgroms mismatch model. The main purpose of our methodology is to convey the design to reach a good trade-off between area and mismatch. Implemented in standard 0.35mum CMOS technology, the circuit also includes a straightforward 4-bits trimming circuit to achieve more process variations independence. Its Monte Carlo temperature coefficient average is 40-ppm/degC and the reference output voltage average is 1.230V. The area of the BGR is 400x350mum2 due to our design matching requirements.

A Design Methodology for Matching Improvement in Bandgap References

Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significantly impact manufacture costs by decreasing yield and so by including extra-circuits for adjustment. In this paper we propose a design methodology based on the Pelgroms MOS transistor-mismatching model devices. Our main objective is to calculate the size of each component considering their relation between area and mismatching. Therefore, in order to validate our proposal methodology, we used as a design target a bandgap reference circuit fabricated in 0.35 mum CMOS technology. Its temperature coefficient attains an average value of 40ppm/degC and an average output voltage of 1,20714V. It also includes a straightforward 4-bits trim circuit to achieve more process independence variation. As a result of our methodology, the considerable area of 400 times 350 mum2 was occupied due to our matching design requirements

0.3 V supply, 17 ppm/°C 3-transistor picowatt voltage reference

In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ<; 3.3% and that 90% of the samples present TC<;50 ppm/°C without trimming.

Self-biased CMOS Current Reference based on the ZTC Operation Condition

A self-biased current reference based on the MOSFET Zero Temperature Coefficient (ZTC) condition is presented. It can be implemented in any CMOS process and it provides a simple alternative to design a reference current suitable for low TC biasing. This topology was designed in a 0.18 μm process to generate 5 μA under a supply voltage from 1.4V to 1.8 V, spending a silicon area around 0.010mm2. From circuit simulations, the current reference is estimated to have a temperature coefficient (TCeff ) of 15 ppm/°C from -40 to +85 °C and a fabrication sensitivity of σ/μ = 4.5%, including average process and local mismatch variability. The power supply sensitivity resulted around 1%V for this new reference.

0.7 V supply, 8 nW, 8 ppm/°C resistorless sub-bandgap voltage reference

In this work a new resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere consumption range, and under 1 V of power supply. The behavior of the circuit is analitically described, a design methodology is proposed and simulation results are presented for a standard 0.18 μm CMOS proCess. A reference voltage of 463 mV is demonstrated, with a temperature coefficient of 8 ppm/°C for the 0 to 125 °C range, while the power consumption of the whole circuit is 8.25 nW under a 0.75 V power supply at 27 °C. The estimated silicon area is 0.0043 mm2.

0.9 V, 5 nW, 9 ppm/ o C resistorless sub-bandgap voltage reference in 0.18μm CMOS

In this work a novel resistorless sub-bandgap voltage reference (BGR) is introduced. It is a self-biased and small area topology that works in the nano-ampere current consumption range, and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a standard 0.18 μm CMOS process are analysed. A reference voltage of 479 mV is demonstrated, with a temperature coefficient of 8.79 ppm/°C for the 0 to 125°C range, while the power consumption of the whole circuit is 4.86 nW under a 0.9 V power supply at 27 oC. The estimated silicon area is 0.0012 mm2.

A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference using zero- V T active loads

A low-voltage high-PSRR CMOS voltage reference operating with picowatt power consumption is presented. The voltage reference is generated from the threshold voltage (VT) difference of two transistors biased in weak inversion. The VT difference is achieved through its dependence with the transistor dimensions. The high-PSRR is obtained using zero-VT transistors as active loads. The final circuit was designed in a 130 nm CMOS process and occupies around 0.0007 mm2 of silicon area while consuming just 18.5 pW at 27°C. Post-layout simulations present a 62 mV reference voltage with a temperature coefficient of 15 ppm/°C, for a temperature range from -25 to 125 °C and a Power Supply Rejection Ratio (PSRR) of -68.7 dB at 0.3 V of supply voltage.

Resistorless switched-capacitor current reference based on the MOSFET ZTC condition

The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and voltage references. This condition is usually analyzed using the strong inversion quadratic MOSFET model. In this work we use a different approach, based on a continuous MOSFET model that can predict its behavior from weak to strong inversion. Based on this analysis, we verify that the ZTC point occurs from moderate to strong inversion for any CMOS process, since this point must occur for gate-source voltages larger than one threshold voltage. Also, a resistorless switched capacitor current reference based on the ZTC condition (ZSCCR), presenting low temperature coefficient (TC), is presented. The ZSCCR is designed in a 180 nm process, resulting a reference current of 5.88 μA under a supply voltage of 1.8 V, and occuping a silicon area around 0.010mm2. Results from circuit simulation show an effective temperature coefficient (TCeff ) of 60 ppm/°C from -45 to +85 °C and a power consumption of 63 μW.

2.3 ppm/°c 40 nW MOSFET-only voltage reference

A MOSFET-only sub-bandgap voltage reference at less than 50 nW and with very low temperature coefficient is introduced. It consists of a threshold voltage extractor circuit and a proportional to absolute temperature voltage generator, using no resistors. The behavior of the circuit is analytically described, a design methodology is proposed and simulation results for a 0.13μm CMOS process are presented. It allows a reference voltage below the bandgap, 625 mV in this design example, achieving a temperature coefficient of 2.3 ppm/°C for the -40 to 125 °C temperature range. The circuit consumes 40 nW at 27 °C and under 1.2 V supply, being the implemented silicon area 0.0099 mm2.

A 0.45 V, 93 pW temperature-compensated CMOS voltage reference

This paper presents a self-biased self-cascode MOSFET (SBSCM) voltage reference that can operate with supply voltages as low as 0.45 V while consuming tens of pW. The voltage reference is generated through the self-cascode MOSFET (SCM) using transistors with different threshold voltages and is implemented in a way that the SCM itself composes the bias circuitry. The proposed topology was implemented in a standard 0.18 μm CMOS process and post-layout simulation results in a reference voltage of 248 mV with temperature coefficient around 7 ppm/oC for the 0 oC to 125 oC range, while consuming 93 pW at room temperature with 0.45 V of supply voltage. The occupied silicon area is 0.002 mm2.