Sergio Camerlo

Signal link-path characterization up to 20 GHz based on a stripline structure

Dielectric properties and losses are two critical issues in signal link-path characterization. To obtain the substrate dielectric properties for a planar transmission line, an analytical solution is derived and validated based on a stripline structure and measured scattering parameters with TRL de-embedding. The characterized dielectric property is used to evaluate dielectric loss and conductor loss. The total loss is thereby found from their summation. The calculated total loss is compared to the measured total loss, and the conductor loss and dielectric loss are then quantifiable. Since the conventional description using the loss tangent and dielectric constant to represent material properties is usually insufficient as the frequency reaches 20 GHz, a Debye model is proposed. The second order Debye parameters are subsequently extracted using a genetic algorithm. A full wave simulation is implemented to verify the determination of two-term Debye model parameters.

The implementation of ASIC packaging design and manufacturing technologies on high performance networking products

This paper briefly presents how silicon integration and advances in packaging technology have enabled higher performance networking products, and is followed by discussions of how a system-level integrated approach is needed to address the challenges of the next generation products. Different methodologies of integrating memory and ASIC using advanced packaging technologies at both package level and board-/system-level are presented. Both connector-based and SMT based system in package (SiP) solutions with either flip-chip bare-die or BGA technologies are evaluated. Impact of each technology on product designs at silicon, substrate, and board level, as well as the effects on product manufacturability and reliability are discussed.

Improving signal integrity of system packaging by back-drilling plated through holes in board assembly

The development and deployment of very fast signaling technologies for communication across the backplane has introduced the need for a multidisciplinary design approach where the performance of the silicon to silicon communication channel is addressed from a variety of different perspectives. SerDes technology, connectors, vias, via stubs, and board materials are among the elements that need to be considered and modeled to reach-the desired trade off with respect to performance, cost and quality. In this study, component and system level electrical performance with back-drilled (or Counter Bored) Plated Through Holes is investigated, with simulation and testing examples. The methodology that is presented leverages multidisciplinary aspects of design and puts quality as a key ingredient of the development process. The results of this work and the associated methodology have been successfully shared across Business Units and Technology Groups.

Effects of Void, Crack, and PCB Thickness on the Solder Joint Reliability of Wafer-Level Chip-Scale Package (WLCSP) Assemblies

The creep analyses of solder-bumped wafer-level chip-scale package (WLCSP) on printed circuit board (PCB) subjected to temperature cycling loading are presented. Emphasis is placed on the effects of PCB thickness on the solder joint reliability of the WLCSP assembly. Also, the effects of crack-length on the crack tip characteristics such as the J-integral in the WLCSP solder joint are studied by the fracture mechanics method. Finally, the effects of voids on the crack growth in the WLCSP solder joint are investigated.Copyright