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Dive into the research topics where Wheling Cheng is active.

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Featured researches published by Wheling Cheng.


IEEE Transactions on Electromagnetic Compatibility | 2008

Reconstruction of Dispersive Dielectric Properties for PCB Substrates Using a Genetic Algorithm

Jianmin Zhang; Marina Y. Koledintseva; James L. Drewniak; David Pommerenke; Richard E. DuBroff; Zhiping Yang; Wheling Cheng; Konstantin N. Rozanov; Giulio Antonini; Antonio Orlandi

An effective method for extracting parameters of a Debye or a Lorentzian dispersive medium over a wideband frequency range using a genetic algorithm (GA) and a transmission-line model is presented. Scattering parameters (S-parameters) of the transmission-line sections, including a parallel plate, microstrip, and stripline, are measured. Wave equations for TEM/quasi-TEM mode with a complex propagation constant and a frequency-dependent wave impedance are used to evaluate the corresponding S-parameters in an analytical model. The discrepancy between the modeled and measured S-parameters is defined as the objective function in the GA. The GA is used for search of the dispersive-medium parameters by means of minimizing the objective function over the entire frequency range of interest. The reconstructed Debye or Lorentzian dispersive material parameters are corroborated by comparing the original measurements with the FDTD modeling results. The self-consistency of the proposed method is demonstrated by constructing different test structures with an identical material, i.e., material parameters of a substrate extracted from different transmission-line configurations. The port effects on the material parameter extraction are examined by using through-reflection-line calibration.


international symposium on electromagnetic compatibility | 2006

Signal link-path characterization up to 20 GHz based on a stripline structure

Jianmin Zhang; James L. Drewniak; David Pommerenke; Richard E. DuBroff; Zhiping Yang; Wheling Cheng; John Fisher; Sergio Camerlo

Dielectric properties and losses are two critical issues in signal link-path characterization. To obtain the substrate dielectric properties for a planar transmission line, an analytical solution is derived and validated based on a stripline structure and measured scattering parameters with TRL de-embedding. The characterized dielectric property is used to evaluate dielectric loss and conductor loss. The total loss is thereby found from their summation. The calculated total loss is compared to the measured total loss, and the conductor loss and dielectric loss are then quantifiable. Since the conventional description using the loss tangent and dielectric constant to represent material properties is usually insufficient as the frequency reaches 20 GHz, a Debye model is proposed. The second order Debye parameters are subsequently extracted using a genetic algorithm. A full wave simulation is implemented to verify the determination of two-term Debye model parameters.


international symposium on electromagnetic compatibility | 2009

Investigation of mixed-mode input impedance of multi-layer differential vias for impedance matching with traces

Hanfeng Wang; Wheling Cheng; Jianmin Zhang; John Fisher; Lin Zhu; James L. Drewniak; Jun Fan

In multilayer printed circuit boards (PCBs), vias are commonly used to connect traces on different signal layers. This paper derives the mixed-mode input impedance of differential vias in typical multilayer structures, and proposes to use the input impedance concept to achieve impedance matching at the via and trace connections. Effects of several geometrical parameters on the input impedance of differential vias have also been studied in this paper. This method can be used to optimize via structures in PCB design processes for smooth via-trace transitions.


electronic components and technology conference | 2005

The implementation of ASIC packaging design and manufacturing technologies on high performance networking products

Sergio Camerlo; Jie Xue; Wheling Cheng; Rosalynn Duong; Bangalore J. Shanker; Yida Zou; Mudasir Ahmad; Mark Brillhart; Ken Hubbard; Scott Priore

This paper briefly presents how silicon integration and advances in packaging technology have enabled higher performance networking products, and is followed by discussions of how a system-level integrated approach is needed to address the challenges of the next generation products. Different methodologies of integrating memory and ASIC using advanced packaging technologies at both package level and board-/system-level are presented. Both connector-based and SMT based system in package (SiP) solutions with either flip-chip bare-die or BGA technologies are evaluated. Impact of each technology on product designs at silicon, substrate, and board level, as well as the effects on product manufacturability and reliability are discussed.


Archive | 2008

Method for fabricating a printed circuit board having a coaxial via

Wheling Cheng; Roger Karam; Sergio Camerlo


Archive | 2006

Coaxial via in PCB for high-speed signaling designs

Wheling Cheng; Roger Karam; Sergio Camerlo


international symposium on electromagnetic compatibility | 2008

Differential vias transition modeling in a multilayer printed circuit board

Matteo Cocchini; Wheling Cheng; Jianmin Zhang; John Fisher; Jun Fan; James L. Drewniak; Yaojiang Zhang


international symposium on electromagnetic compatibility | 2005

A hybrid approach to decrease port influence in transmission line characterization

Jianmin Zhang; David Pommerenke; James L. Drewniak; Richard E. DuBroff; Zhiping Yang; Wheling Cheng; John Fisher; Sergio Camerlo


Archive | 2003

Methods and apparatus for testing a circuit board using a surface mountable adaptor

Bangalore J. Shanker; Suryaprakash Jonnavithula; Ashwath Nagaraj; Wheling Cheng


Archive | 2012

PCB for high-speed signaling designs

Wheling Cheng; Roger Karam; Sergio Camerlo

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James L. Drewniak

Missouri University of Science and Technology

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Richard E. DuBroff

Missouri University of Science and Technology

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Jun Fan

Missouri University of Science and Technology

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