Sérgio J. M. de Almeida

Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-2m Array Multipliers

In this paper, we introduce new dedicated blocks for radix-2 m multiplication. These blocks are basic components of the structure of the 2´s complement radix-2 m array multiplier previously proposed in the literature. In the original array multiplier, the blocks that perform the radix-2 m multiplication were automatically synthesized from a truth table. The dedicated multiplication blocks we propose are themselves composed of a structure of less complex multiplication blocks and resort to efficient Carry Save adders (CSA). This new scheme can be naturally extended for different radices multiplication. We present results of area, delay and power consumption for 16, 32 and 64 bit array multipliers using the new dedicated modules. The results show that by using the new dedicated modules, the array multipliers are more efficient in terms of delay and power consumption when compared both against the original array structure and the Modified Booth multiplier.

Fixed-point adaptive filter architecture for the harmonics power line interference cancelling

This paper presents a dedicated architecture for Least Mean Square (LMS) adaptive filtering algorithm for the harmonics power line interference cancelling. The proposed structure was developed targeting operations on fixed point what leads to less complex design. The proposed architecture was described in VHDL, and the results indicate that it is able to cancel efficiently the interferences in the fundamental frequency, and its high order harmonics. This aspect shows the efficiency of our solution over previously proposed prominent solutions that only focus on the cancelling of the fundamental frequencies.

Gray encoded fixed-point LMS adaptive filter architecture for the harmonics power line interference cancelling

This paper proposes the implementation of dedicated hardware architecture for the Least Mean Square (LMS) adaptive filtering algorithm by using Gray encoding arithmetic operators, whose main goal is to cancel the interferences in the signal of interest. In the used scheme, from a 60Hz reference signal, the algorithm is able to estimate the superior harmonics, using after these results for the cancelling of interferences related to the signal of interest. One of most widely used technique for the switching activity reduction uses signal encoding. In this work, the proposed adaptive filtering architecture uses a Hybrid encoding in its data buses, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. The main results showed that the Hybrid multipliers are more efficient than the Binary ones, by presenting less power consumption in some cases. Moreover, the implemented adaptive filtering architectures were validated and compared in both Binary and Hybrid encoding. The efficiency of the implemented Hybrid filter for the cancelling of interferences was proved by reducing more power than the Binary one. By the results, we conclude that it could be practicable to implement an adaptive filtering architecture operating on Hybrid encoding.

A stochastic model for the deficient order Affine Projection algorithm

This paper presents a statistical analysis of the Affine Projection (AP) adaptive algorithm for autoregressive (AR) input signals when the order of the AP algorithm is smaller than the order of the AR process. Deterministic recursive equations are derived for the mean weight and mean-square error behavior. Monte Carlo simulations show excellent agreement with the theoretical predictions in steady-state and, under certain conditions, during transient. These results are of special interest in practical applications where the computational complexity prevents implementation of the sufficient order AP algorithm for high order AR inputs.

Design of an efficient FPGA-based interference canceller structure using NLMS adaptive algorithm

This paper presents fixed-point dedicated architecture of NLMS (Normalized Least Mean Square) adaptive filtering algorithm for the harmonics power line interference cancelling. The NLMS is the normalized version of the LMS algorithm, whose main characteristics are related to the increase of speed of adaptation, and low sensitivity to the power reference signal. The developed architecture was described in VHDL and synthesized to FPGA. Synthesis results indicate that the interference canceller based on NLMS filter is able to efficiently cancel the interferences in the fundamental frequency, and its high order harmonics, with faster convergence speed than the previously proposed prominent solution that uses the LMS adaptive filter.

Architectural exploration of Forward 4×4 Hadamard Transform applied to H.264/AVC video compression standard

The focus of this work is the improvement of performance of the encoder of the H.264/AVC by exploiting different architectural alternatives for the Forward 4×4 Hadamard Transform. This transform module is present in the critical path for the video compression that uses intra-frame encoding in H.264/AVC standard. Combinational and sequential architectures are proposed for the calculation of the Hadamard transform algorithm. As this transform is composed by a great amount of addition operation, efficient adder compressors are used in order to achieve a higher performance in the proposed architectures. A combination of 4∶2, 8∶2 and 16∶2 adder compressors, are used in the combinational and sequential architectures. The architectures were all described in VHDL and synthesized to TSMC 0.18µm CMOS standard cell. Synthesis results indicate that the architectures with 16∶2 adder compressor reach the best performance results. While the use of this compressor enables a reduction of 17% of delay value in the combinational architecture, the frequency operation of the sequential architecture can be improved by almost 3 times, with a reduced latency, when using this adder compressor.

Exploiting architectural solutions for IIR filter architecture with truncation error feedback

Digital filters are widely used in digital systems, which can make use of integer arithmetic to achieve higher performance. The use of integer operands can compromise the filter operation, due to the inherently error caused by truncation operations. Addressing this kind of problem, we propose an IIR filter for biomedical signals using the truncation error feedback (TEF), in which a feedback signal is obtained from the division remainder of the truncation operation. Two dedicated fully-sequential and parallel architectures were implemented and simulated using VHDL language, and synthesized in Cadence environment using the 45 nm Nangate Open Cell Library. A simulated ECG signal was used as input to verify the functionality of an IIR high pass filter with TEF. The results of our analysis indicate that the use of TEF can be an important approach in digital systems, where integer arithmetic for computation is adequate for performance requirements. Using this feedback signal, the design specifications of the filter remained significantly the same compared to the filter specification, independently of the cut-off and sample frequency ratio.

Power efficient 2-D rounded cosine transform with adder compressors for image compression

This work proposes a dedicated hardware design for 2-D Rounded Cosine Transform (RCT), using efficient adder compressors, and discusses comparisons with Discrete Cosine Transform (DCT). The RCT is an approximation of the cosine function, whose resultant matrix is only composed of 0 and 1 values. Therefore, the RCT can be easily implemented by using only adders/subtractors. In this work, we use combinations of efficient 4-2, 6-2 and 8-2 adder compressors for the RCT implementation. The RCT performance combined with its lower computational complexity makes this transform an excellent choice for a dedicated hardware for image compression. We present an environment, whose synthesis reports are based on a set of true images as input vectors in order to obtain valid power results. The results show that the RCT hardware solution with adder compressors minimizes both cells area and power consumption with good overall quality images.

A composite hypothesis test for active weight detection in sparse system identification

Adaptive sparse system identification can profit from specialized algorithms that detect and adapt only the weights corresponding to the nonzero coefficients of the unknown impulse response. This leads to adaptive identification with reduced computational complexity and faster convergence. Most real-time sparse system identification algorithms which follow this strategy neglect prior information on the adaptive weight activity. Thus, the probabilities of a given weight to be active (nonzero) or not are assumed to be equal at each detection step. This paper proposes a Bayesian composite hypothesis test for detecting active weights. The prior probabilities of the active and non-active weights are adjusted from previous decisions and used to evaluate the decision threshold. The proposed hypothesis test is employed on a well known sparse system identification algorithm. The results indicate the improvements that can be achieved using the proposed Bayesian approach.

High performance Haar Wavelet transform architecture

This paper proposes high performance dedicated hardware architecture for the Haar Wavelet transform, whose structure is based on nine levels of decomposition. The architecture is described in hardware description language VHDL, and it has been designed by using fixed point arithmetic, and also using efficient arithmetic operators into their sub modules. The efficiency of the architecture was proved by showing that the error from both the signals of the architecture and the signals from a reference model, described in float point in the MATLAB® environment, is negligible. Moreover, the synthesis results clearly show the higher performance of the proposed architecture over other solutions from the literature, where gains in terms of frequency operation and area utilization are reported.