Seung-Kwon Paek

A MODE-CHANGEABLE 2-D DCT/IDCT PnOCESSOR FOR DIGITAL VCR

In a digital VCR, the DCT/IDCT is performed by both the 8/spl times/8 mode and the 2/spl times/4/spl times/8 mode to improve the coding efficiency. A new 2-D DCT/IDCT processor which requires minimal hardware overhead for 8/spl times/8/2/spl times/4/spl times/8 mode change for a digital VCR is presented. The proposed DCT/TDCT processor uses a concurrent architecture and executes both the DCT and IDCT with 8/spl times/8 and 2/spl times/4/spl times/8 mode selection. This chip is implemented on the basis of the row-column decomposition scheme. The proposed architecture minimizes the hardware overhead for the 2/spl times/4/spl times/8 mode by sharing the same data path with the 8/spl times/8 mode as much as possible. The proposed architecture also reduces the hardware and the chip size by exploiting the table look-up method instead of the extra multiplication circuits in the weighting coefficients handling. The implemented DCT/IDCT processor satisfies the accuracy specification of digital VCR.

A real-time wavelet vector quantization algorithm and its VLSI architecture

A real-time wavelet image compression algorithm using vector quantization and its VLSI architecture are proposed. The proposed zerotree wavelet vector quantization (WVQ) algorithm focuses on the problem of how to reduce the computation time to encode wavelet images with high coding efficiency. A conventional wavelet image-compression algorithm exploits the tree structure of wavelet coefficients coupled with scalar quantization. However, they can not provide the real-time computation because they use iterative methods to decide zerotrees. In contrast, the zerotree WVQ algorithm predicts in real-time zero-vector trees of insignificant wavelet vectors by a noniterative decision rule and then encodes significant wavelet vectors by the classified VQ. These cause the zerotree WVQ algorithm to provide the best compromise between the coding performance and the computation time. The noniterative decision rule was extracted by the simulation results. Moreover, the zerotree WVQ exploits the multistage VQ to encode the lowest frequency subband, which is generally known to be robust to wireless channel errors. The proposed WVQ VLSI architecture has only one VQ module to execute in real-time the proposed zerotree WVQ algorithm by utilizing the vacant cycles for zero-vector trees which are not transmitted. And the VQ module has only L+1 processing elements (PEs) for the real-time minimum distance calculation, where the codebook size is L. L PEs are for Euclidean distance calculation and a PE is for parallel distance comparison.

Semi-recursive VLSI architecture for two dimensional discrete wavelet transform

This paper presents an efficient two-dimensional discrete wavelet transform (2-D DWT) VLSI architecture which calculates the 2-D DWT for image processing in real-time. The proposed architecture, semi-recursive 2-D DWT VLSI architecture, has the minimum H/W cost of internal word length, data-bus utilization, scheduling control overhead and storage size. Compared with the conventional recursive 2-D DWT VLSI architecture, the size of multipliers and registers are reduced by 13% and 34% respectively. Furthermore, the semi-recursive 2-D DWT VLSI architecture exploits the lapped block processing and hence has the minimum transposition storage size and short latency.

Rate control strategy based on human visual sensitivity for MPEG video coder

The Moving Picture Experts Group (MPEG) has standardized the bit-stream syntax for the coded representation of video. This means that MPEG specifies only a decoding method and allows much flexibility in encoding methods. Therefore the picture quality of the reconstructed video sequences is considerably dependent on the rate control strategy in the encoding method. We propose a new rate control strategy conforming to the MPEG syntax that improves the reconstructed picture quality. The new rate control strategy allocates the target number of bits and assigns quantization step sizes adaptively based on the human visual sensitivity and the complexity of the picture to be coded. The proposed rate control strategy consists of the following steps. First, a 16 X 16 macroblock is classified into one of 8 macroblock classes based on human visual sensitivity for luminance and color components in the macroblock and then an 8 X 8 block is classified into one of block classes by its variance. Next, the target number of bits is allocated to a block and the quantization step size is assigned to a macroblock. The result of subjective tests showed the proposed rate control strategy improved the picture quality of the reconstructed video sequences considerably over the conventional strategy. Especially in the proposed strategy, the subjective picture quality between frames was more constant and hence was less degraded than conventional rate control strategies.