Seung-Man Choi

An experimental study on the TSV reliability: Electromigration (EM) and time dependant dielectric breakdown (TDDB)

TSV is the key component in fabricating 3-D ICs which can bring lower power consumption, higher integration density and shorter interconnection length. Very few works on EM and TDDB of TSV have been done. Thus, TSV macros with BEOL and backside metal were designed and tested adventurously with EM and TDDB reliability perspective. For EM, the void, however, was found at Cu/SiN interface between TSV bottom and backside metal not at TSV itself due to unexpectedly strong reliability of TSV. And also the TDDB occurred at IMD not at TSV dielectric oxide layer. As a result, the minimum level of reliability of TSV has been obtained experimentally in silicon data at least although the reliability of TSV itself has not been assessed exactly. The guide lines for making reliability macros and testing conditions are suggested also by further investigation.

Superfilling CVD of copper using a catalytic surfactant

Chemical vapor deposition of copper using iodine as catalytic surfactant fills sub-micron holes and trenches in bottom-up fashion and results in a leveled film surface. Accelerated film growth in holes and trenches seems due to the accumulation of the catalytic surfactant at the bottom of the holes and trenches caused by the reduction of surface area during the film growth. High growth rate and good filling and leveling capability make this deposition method a strong candidate for manufacturing metal interconnects for next-generation microelectronic devices. It suggests that use of surfactants may enable other applications previously considered not viable in vacuum deposition.

Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.

A practical modeling for transient thermal characteristics of multilevel interconnects

In this study, intuitive is given on time-dependent thermal characteristics in multilevel interconnects subjected to carry either DC or pulsed-DC. FEM simulation is employed to model the propensity of temperature profile with respect to the variety of interconnects having different geometrical features in terms of metal width, metal height and distance between metal and Si substrate. Accordingly, a practical model that enables to prognosis temperature increase resulting from current-driven metal interconnects and temperature decrease after current carried along metal line stops is developed. It is found that a proposed model precisely predicts thermal transient arisen from metal interconnect, regardless of geometrical factors of metal dimension and location. In addition, transient thermal behavior of metal interconnects carrying pulsed DC with various frequencies is investigated. A circuit designer is required to adjust the maximum allowable current carried along metal interconnects according to the frequency of pulsed DC as well as geometrical dimensions of metal interconnects. Hence, robustness in circuit design even in the earlier stage of development phase can be accomplished for metal interconnects by suppressing electromigration and rupture caused by thermal transient.

A modified berman model for the prediction of time-dependent dielectric breakdown (TDDB) characteristics of low-k/ULK interconnect dielectrics from dual-voltage ramp dielectric breakdown (DVRDB) test

We present a modified Berman model that relates breakdown voltage distributions, from dual voltage ramp dielectric breakdown (DVRDB) test, to the distribution of time-to-fail (TTF) during constant voltage stress (CVS) conditions, assuming that dielectric failure behavior under a constant voltage stress follows the square-root E-model. The methodology presented in this work demonstrates a fast and very effective way of extracting the voltage acceleration parameter (i.e., electric field dependence) and predicting TTF under CVS TDDB test conditions. Both low-k (k=3D2.7) and ULK(k<2.5) DVRDB and CVS TDDB data of 45nm and 32nm dielectrics are presented, along with the model predictions and Monte-Carlo simulation results.

Process integration of CVD Cu as a seed layer for Cu electroplating and a plug-fill application

CVD Cu film has been evaluated as a seed layer for Cu electroplating and a plug-fill application for back-end Cu metallization in 0.18 /spl mu/m technologies. Excellent step coverage and via plug-fill with CVD Cu were routinely obtained. CVD Cu film showed the enhanced seed layer performance compared to an ionized PVD Cu seed layer. It was found that only 40 /spl Aring/ PVD Cu interlayer between the TaN and CVD Cu layer is enough to obtain low via contact resistance. The scheme of the CVD Cu seed formation followed by Cu electroplating showed approximately 20% lower via resistance as compared to that of the CVD Cu plug-fill followed by Cu electroplating.

Metal bit-line common contact integration technology in 0.17 /spl mu/m-DRAM and merged DRAM in logic devices

The metal bit-line common contact (MBCC) process has been successfully integrated in 0.17 /spl mu/m DRAM and in merged DRAM in logic devices. By introducing in-situ i-PVD Ti-TiN on W-plug MBCC, reliable electrical performance, P/sup +/ R/sub c/<1000 /spl Omega//cnt and N/sup +/ R/sub c/<500 /spl Omega//cnt without leakage, and process stability are achieved after thermal treatment at 750/spl deg/C for 100 min.