Ho-Kyu Kang

Reliability of CVD Cu buried interconnections

CVD Cu, which is both highly conductive and reliable, has been investigated as an interconnection material. Cu/sup 1+/ (hfac)(tmvs) is the precursor used in this work. Excellent conformality, which is required for reliable high aspect ratio buried interconnection, has been observed and quantified by simulations. Cu diffusion through TiW as thin as 25 nm has been investigated using large area diodes. Drift of Cu through various dielectrics has been observed, demonstrating the necessity of diffusion barriers. Electromigration studies indicate that Cu interconnections are more reliable than Al alloys.<<ETX>>

CVD Cu interconnections for ULSI

CVD Cu has been investigated as an interconnection material. The Cu films have excellent step coverage due to the very low sticking coefficient of 0.015 of the precursor, Cu/sup 1+/(tmvs) (hfac). High aspect ratio trenches and vias can be conformally filled without formation of keyholes. Using etchback processes, lines and plugs can be formed. At temperatures typically encountered in back-end processing, no significant diffusion of Cu through several commonly used inter-metal dielectrics and TiW is observed. CVD Cu interconnections have been incorporated into a CMOS process. No degradation in device characteristics due to Cu is detected.<<ETX>>

A highly manufacturable, low-thermal budget, void and seam free pre-metal-dielectric process using new SOG for beyond 60nm DRAM and other devices

New PMD (Pre-Metal Dielectric) process by employing polysilazane based inorganic SOG (spin-on-glass) is suggested for future VLSI devices. Compared with conventional SOG materials, the film made from new SOG has higher wet etch resistance, which is critical in achieving deformation-free contact profile. Additional advantages of using this new SOG process are excellent gap-fill capability upto an aspect ratio (A/R) of 20 and lower thermal budget than BPSG reflow process. Neither detrimental effect of new SOG PMD process on electrical characteristics nor device performance such as refresh characteristic, compared to HDPCVD SiO/sub 2/ was observed, indicating this is a PMD process of choice for the future devices.

Reliability of chemically vapor deposited (CVD) copper interconnections

The reliability issues of chemically vapor deposited copper interconnections for applications in integrated circuits are discussed. The void-free conformal deposition of copper films into high aspect ratio trenches and via holes is demonstrated. The effectiveness of various dielectrics and metals as diffusion and drift barriers is compared. The electromigration properties of different copper interconnection structures and the dependence on microstructures, current densities and temperatures are evaluated.

Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.

Alleviating electromigration through re-engineering the interface between Cu & dielectric-diffusion-barrier in 90 nm Cu/SiOC (k=2.9) device

Despite the initial success in integrating a 90 nm Cu/SiOC (k=2.9) device using the HSQ via-filler scheme, the reliability issues remain. By correlating electromigration (EM) with the moisture blocking capability of the dielectric-diffusion-barrier, we target the factors contributing to the moisture blockage, namely, the N and H-content within SiC. Consequently, increasing the N/H ratio in the SiCN film, we demonstrated a significant enhancement in EM reliability.