Bong-seok Suh

Advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects

An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.

Re-defining reliability assessment per new intra-via Cu leakage degradation

By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.

Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.

Process integration of CVD Cu seed using ALD Ru glue layer for sub-65nm Cu interconnect

Chemical-vapor-deposited(CVD) Cu film was successfully demonstrated as a seed layer for Cu electroplating, by using atomic-layer-deposited(ALD) Ru as a glue layer on ALD WNC barrier metal. Low via resistance of below 3/spl Omega//via was obtained in 0.13 /spl mu/m via chains, which was built in SiOC (k=2.9) intermetal dielectric. The adhesion between WNC and CVD Cu. estimated by mELT, was significantly improved by the insertion of ALD Ru and HR-XTEM analysis showed no interfacial layers at both Cu/Ru and Ru/WNC interfaces. In addition, Ru was found to promote the 2-D planar growth of CVD Cu film rather than the 3-D island growth.

Effect of mechanical strength and residual stress of dielectric capping layer on electromigration performance in Cu/low-k interconnects

We present the effect of mechanical strength and residual stress of dielectric barrier on electromigration performance in Cu/low-k interconnects. It has been discovered that mechanical strength and residual stress of dielectric capping layer have a great role on EM performance. The use of mechanically strong dielectric capping material with high residual compressive stress in Cu/low-k interconnects improves a structural confinement of Cu line. Also, it helps tensile stress level decrease near via bottom and compressive stress level increase at Cu beneath SiCN along Cu line. Reduction of tensile stress at via bottom would effectively suppress void nucleation and growth. Moreover, increase of compressive stress in Cu beneath SiCN alleviates Cu migration through that pathway, leading to a longer lifetime of interconnect component.