Seunghyun Lim

A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs

This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 times 240 pixels has been fabricated with a 0.35-mum CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mus , which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.

A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1–4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2–6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.

Switched capacitor circuit

A without increasing steady bias current, realizing a switched capacitor amplifier circuit together to enable fast settling time characteristic rise and fall of the output signal. The apparatus includes input transistors M1 and amplifier 1 having a load transistor M2, a feedback capacitance CF1 first terminal connected to the amplifier input Ain, a switch SW1 provided between the amplifier input and output, a feedback capacitor CF1 the input signal voltage Vin 2 terminal with sampling period, the switched-capacitor circuit of the switch SW2 to connect the amplifier output Aout in the read period and the basic structure, further between the gate of the second terminal and the load transistor M2 of the feedback capacitance CF1 the second provided with a feedback capacitance CF2 for, a switch SW3 to cut during readout gate bias circuit 2 of the load transistor M2 to. .FIELD 1

A 5000S/s Single-Chip Smart Eye-Tracking Sensor

This paper proposes a high-speed single-chip eye tracker that eliminates the effect of the glint and generates the digital address for the center of the pupil.

Smart CMOS Image Sensor With High SBR and Subpixel Resolution for Light-Section-Based Range Finding

Light-section (LS)-based range finders are commonly used for obstacle recognition in home service robots and autonomous vehicles. This paper proposes a smart CMOS image sensor for LS-based range finding. The proposed sensor can detect the laser light, even under very strong ambient-illumination levels by using a multiple-capture frame-correlated double sampling (F-CDS), which is realized with an inverter-based switched-capacitor F-CDS accumulator. The proposed sensor also includes on-chip winner-take-all circuits that significantly reduce the software and hardware complexity of interpolation for the subpixel resolution. The prototype chip was fabricated using a 0.35-mum CMOS process. The measurement results show that the proposed sensor can detect a laser line with an intensity that is 56.5 dB lower than that of the ambient illumination, providing a spatial resolution of plusmn0.16 pixels.

A complementary metal-oxide-semiconductor image sensor with analog gamma correction using a nonlinear single-slope analog-to-digital converter

An image sensor has limited dynamic range while the human eye has a logarithmic response over a wide range of light intensity. Although the sensor gain can be set high to identify details in darker areas on an image, this high gain results in saturation in brighter areas. Therefore, gamma correction is essential to match the human eye response. However, the digital gamma correction degrades image quality, especially for darker areas on the image, due to the limited resolution and dynamic range of the analog-to-digital converter (ADC). In this paper, we propose a complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) with a compact nonlinear ADC which performs analog gamma corrections that use the full dynamic range. A CIS with the proposed nonlinear ADC was fabricated with a 0.35-µm CMOS process. The test results show that the analog gamma correction provides a 2.2 dB peak-signal-to-noise-ratio (PSNR) improved image quality, which is better than conventional digital gamma corrections.

A 1.5V mixed signal biomedical SOC for implantable cardioverter defibrillators

This paper presents a mixed signal biomedical system implanted in human body to deliver appropriate therapies for atrial tachycardia and fibrillation. The diagnosis of the heart conditions is made with atrial electrograms (EGMs) sensed from within the heart. The system consists of three main parts: 4th order band-pass filter, ADC, and bio-signal processor. All parts are incorporated into a single chip. The chip is fabricated in a 0.35 μm CMOS technology. The chip area is 3.8 x 2.7 mm2.