Stephan Paredes

Toward five-dimensional scaling: how density improves efficiency in future computers

We address integration density in future computers based on packaging and architectural concepts of the human brain: a dense 3-D architecture for interconnects, fluid cooling, and power delivery of energetic chemical compounds transported in the same fluid with little power needed for pumping. Several efforts have demonstrated that by vertical integration, memory proximity and bandwidth are improved using efficient communication with low-complexity 2-D arrays. However, power delivery and cooling do not allow integration of multiple layers with dense logic elements. Interlayer cooled 3-D chip stacks solve the cooling bottlenecks, thereby allowing stacking of several such stacks, but are still limited by power delivery and communication. Electrochemical power delivery eliminates the electrical power supply network, freeing valuable space for communication, and allows scaling of chip stacks to larger systems beyond exascale device count and performance. We find that historical efficiency trends are related to density and that current transistors are small enough for zetascale systems once communication and supply networks are simultaneously optimized. We infer that biological efficiencies for information processing can be reached by 2060 with ultracompact space-filled systems that make use of brain-inspired packaging and allometric scaling laws.

Heat-removal performance scaling of interlayer cooled chip stacks

Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm2. The implementation of 100µm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at 1bar pressure drop with water as coolant for 250W/cm2 hot-spot and 50W/cm2 background heat flux. The total power removed was 390W which corresponds to a 3.9kW/cm3 volumetric heat flow.

Flow Boiling of R134a in a Multi-Microchannel Heat Sink With Hotspot Heaters for Energy-Efficient Microelectronic CPU Cooling Applications

This paper focuses on two-phase flow boiling of refrigerant R134a inside a copper multi-microchannel heat sink for microelectronic central processing unit cooling applications. The heat sink is composed of 100 parallel microchannels, 100 μm wide, 680 μm high, and 15 mm long, with 72-μm-thick fins separating the channels. The base heat flux was varied from 2.57 to 189 W/cm2 and the mass flux from 205 to 1000 kg/m2s, at a nominal saturation temperature of 63°C. Over 40 000 local heat transfer coefficients were measured at 35 locations using local heaters and temperature sensors, for which different heat transfer trends were identified. The main ones were that the heat transfer coefficient increased with heat flux and was independent of mass flow rate. Heat transfer coefficients as high as 270 000 W/m K (relative to the base area) were reached, keeping the chip under 85°C with a maximum of 94 kPa of pressure drop, for no inlet subcooling and a coolant flow rate of 1000 kg/m2s.

Direct Waste Heat Utilization From Liquid-Cooled Supercomputers

Chip microscale liquid-cooling reduces conductive and convective resistance thereby improving the efficiency of datacenters by allowing coolant temperatures above the free cooling limit in all climates. This eliminates the need for chillers and allows the thermal energy to be re-used in cold climates. Replacing the combustion processes for secondary users with recycled heat from the datacenter effectively eliminates carbon dioxide emission during the winter season and reduces operating cost throughout the year. The energy balance of emission-reduced datacenters is compared with a classical air cooled datacenter, a datacenter with free cooling in a cold climate zone, and a datacenter with chiller-mediated energy re-use. Hot water cooled datacenters reduce the effective energy cost by almost a factor of two compared to a current datacenter and reduce the carbon footprint by an even larger factor. Our energy re-use concept has been demonstrated in terms of cost and energy savings in a 60°C liquid cooled supercomputer. Additional alternative energy re-use schemes in hot climates for desalination and adsorption cooling allow close to full use of datacenter heat in all climates and all seasons. Output temperatures for these applications compared to space heating need to be 10–20°C higher which becomes possible through hotspot adapted cooling that eliminates mixing of fluids with different temperatures. In addition, interlayer cooled chip stacks allow double sided hotspot optimized cooling even closer to the heat source with low flow rates and low pumping power. This improves the large efficiency gain that becomes possible through 3D chip stacking.Copyright

Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks

Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize the performance of a three tier chip stack with a footprint of 1cm2. The implementation of 100µm pitch area array interconnect compatible heat transfer structures results in a maximal junction temperature increase of 54.7K at 1bar pressure drop with water as coolant for 250W/cm2 hot-spot and 50W/cm2 background heat flux. The total power removed was 390W which corresponds to a 3.9kW/cm3 volumetric heat flow.

Advanced liquid cooling for concentrated photovoltaic electro-thermal co-generation

We demonstrate an advanced packaging approach with an embedded silicon micro-channel water cooler where the photovoltaic cell is electrically connected by a metallization on the silicon substrate. The backside of the silicon substrate contains the micro-machined fluidic channels thereby minimizing the thermal resistance compared to a state — of — the — art package. This leads to a reduced temperature drop between the photovoltaic cell and the coolant, allowing an increase in the temperature of recovered heat. A low-pressure drop split-flow fluid manifold is implemented to distribute the coolant from one single input to the micro-channel array and back from two outlet ports. A thermal resistance of 0.12 cm2K/W was demonstrated, which allows for the removal of 100W/cm2 heat (>1000 suns) at a ΔT of 12K. Direct chip attached silicon coolers enable higher overall concentration factor thereby reducing photovoltaic cell cost. An additional benefit of silicon is its inertness against corrosion and the matching thermal expansion coefficient which allows building of systems with a very long lifetime. The split flow configuration reduces pumping power to about 5% of the system photovoltaic output. More complex manifold micro-channel systems are proposed to minimize the pumping power to a level below 1% and to cool arrays of cells on a single large substrate.

Angle-of-attack investigation of pin-fin arrays in nonuniform heat-removal cavities for interlayer cooled chip stacks

Interlayer cooling removes the heat dissipated by vertically stacked chips in multiple integrated fluid cavities. Its performance scales with the number of dies in the stack and is therefore superior to traditional back-side heat removal. Previous work indicated that pin-fin arrays are ideally suited as through-silicon-via-compatible heat transfer structures. In addition, four-port fluid-delivery and fluid-guiding structures improve the heat-removal performance for the nonuniform power maps of high-performance microprocessor chip stacks. Accordingly, an extension of the porous-media multi-scale modeling approach is presented as an efficient approach for designing nonuniform heat transfer cavities. A tensor description in combination with a look-up table is proposed to physically describe periodic porous media, such as pin-fin arrays, in detail. Conjugate heat and mass transfer sub-domain modeling is performed with periodic boundary conditions to derive the orientation-dependent permeability and angle offset between the pressure gradient and the Darcy velocity direction for pin-fin arrays with a pin diameter of 50 μm and pitch and height of 100 μm. A local permeability minimum at a flow direction of approx. 30° could be identified. At higher velocities, the fluid flow is biased towards the symmetry lines of the pin-fin array. The modeling concept was validated with experimental readings of a nonuniform, double-side-heated single test cavity. The main characteristics of the temperature field with respect to the four-port architecture, the guiding structures, the fluid temperature increase, and the nonuniform power dissipation are predicted correctly. A statistical comparison of power maps with different heat transfer contrast values resulted in a mean accuracy <6% at a maximal standard deviation of 22.2%. Finally, the potential of the four-port architecture for nonuniform power maps with hot spots in the corners was demonstrated.

Dual function heat-spreading and performance of the IBM/ASTRON DOME 64-bit μServer demonstrator

For the IBM-ASTRON DOME μServer project, we are currently building two types of memory DIMM-like form factor compute node boards. The first is based on a 4 core 2.2 GHz SoC and the second on a 12 core / 24 thread 1.8 GHz SoC. Both employ the 64-bit Power instruction set. Our innovative hot-water based cooling infrastructure also supplies the electrical power to our compute node board. We show initial performance results and conclude with the key lessons we have learnt and an outlook on our next activities.

Extended tensor description to design non-uniform heat-removal in interlayer cooled chip stacks

Interlayer cooling is a heat removal concept that scales with the number of stacked tiers. Uniform fluid cavities result only in moderate heat removal performance. A substantial improvement could be expected for nonuniform, hot-spot-aware fluid cavities. Hence, we propose an extension of our multi-scale modeling framework to support nonuniform fluid cavity designs. The chip stack with its cavities and the silicon dies are represented by field-coupled porous and solid domains, respectively. Detailed sub-domain modeling using two pairs of periodic boundary conditions for fully and half populated pin-fin arrays with 100 μm height and pitch was performed. Permeability and convective thermal resistance values with respect to arbitrary flow directions were extracted. These values are used in the chip stack model to predict the mass and the energy transport within the fluid cavity and between the domains, respectively. Three mathematical permeability descriptions are benchmarked against each other and are experimentaly validated. The extended tensor description predicts the mass flow and maximum junction temperature best at an accuracy of better than 20%. We could also demonstrate the extension of interlayer cooling to TSV pitches of 50 μm with hot-spot heat fluxes of up to 250W/cm2 by pin-fin-density modulation and four-port fluid delivery.

Ecological and economical advantages of efficient solar systems

A strategy to optimize the positive climatic effect of solar energy requires a minimization of embodied energy and a maximization of efficiency to compensate for the upward temperature forcing effect of low albedo solar collector surfaces. Climatic effects of low albedo surfaces are related to those of carbon dioxide emissions. The resulting positive climate forcing effect (cooling) then depends directly on the embodied energy, the absorption, and the efficiency of the system. This analysis favors high efficiency CPV, and even more so dual-use HCPVT systems, over low-efficiency flat panel and thin film technologies. The effect is most prominent in large low latitude cities, where urban heat islands and the subsequent demand for cooling negate positive effects of low-efficiency solar installations.