Sewook Hwang

A 0.008

This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18 ^°C/LSB and the maximum inaccuracy of 20 measured samples is less than ±1.5^°C over a temperature range of 0^°C ~ 110^°C. The entire block occupies 0.008 mm² in 65 nm CMOS and consumes 500 μW at a conversion rate of 469 kS/s.

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This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm2 and 0.94 mm2, respectively, in a 0.13 μm 1P8M CMOS process.

500

This paper describes a dynamic voltage and frequency scaling (DVFS) scheme for the dynamic power management (DPM) of the extendable instruction set computing processor. The DVFS circuit comprises a digitally-controlled DC-DC buck converter with a dual VCDL-based ADC and a low-power and low-jitter DLL-based clock generator with self-calibration. The prototype is fabricated in a 0.18-mum CMOS process. The implemented DVS circuit provides a supply voltage from 1.4 V to 1.8 V and the DFS circuit dynamically generates the system clock from 7.5 MHz to 120 MHz according to the workload of the embedded processor. The DVS and DFS circuits occupy 2.72 mm2 and 0.27 mm2 active areas, respectively.

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A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH ΔΣ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of ±0.5% to 3.5% in steps of 0.5% and three modulation frequencies of fm, 2 fm and 3 fm. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 mm2 in a 0.13-μm CMOS process and consuming 23.72 mW at 3.5 GHz.

469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation

Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (Vss) and small I/O capacitance (CIO) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.

A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection

Cameras and image sensors have recently been installed in many portable devices. An image processor and a transceiver are also adopted in multimedia system-on-a-chip to handle the data from the image sensor. A wide input range and flexible data bandwidth are needed for the serial link receiver to deal with various sensor specifications. This paper presents an 11.2-Gb/s low-voltage differential signaling (LVDS) receiver for various portable devices that employ a LVDS system for data transmission between an image sensor and a processor. The designed LVDS receiver has 16 data channels and four clock channels. All the channels are selectively turned on or off, depending on the application. The proposed comparator used for the input driver of the receiver has a rail-to-rail input range and 60 mV of minimum input swing level. The clock dividing ratio and the data de-serializing factor of the proposed receiver are also programmable to deal with various color depths of image sensors. The designed LVDS receiver is fabricated in a 0.13-μm CMOS process, occupying 4-4 mm, with a 7.24-mm2 core. Power consumption is 77.38 mW, when every channel is turned on.

A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI.

A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile

We present a 1.62–5.4-Gb/s receiver for DisplayPort version 1.2a and propose an adaptive equalizer (EQ) with a peak-level comparison technique for eye measurement. A single comparator and an up/down unmatched-current charge pump are used to realize a simpler EQ architecture with low power dissipation. A referenceless frequency acquisition technique is also proposed. A time-to-digital converter-based pulsewidth detector supports the referenceless frequency acquisition within the range of 1.62–5.4 Gb/s. An XOR-gate-embedded charge pump and a half-rate linear phase detector were used to improve the jitter tolerance (JTOL) performance. The measured eye opening of the proposed EQ at 5.4 Gb/s was 0.68 UI with a −20-dB loss channel. The proposed receiver passed all the JTOL tests of the DisplayPort compliance specification version 1.2b. The power consumption of the receiver was 36.8 mW at 5.4 Gb/s. The receiver occupied a core area of 0.265 mm2 using 65-nm CMOS process technology.

17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces

DRAM speed already reaches 7Gb/s/pin for GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator [2]. In general, the sensitivity of PLL to supply noise gives rise to large jitter accumulation. If the supply noise frequency is close to the PLL bandwidth, more jitter peaking occurs. Therefore, the PLL bandwidth is an important parameter to achieve low jitter performance [3]. Crosstalk becomes a crucial issue for over 7Gb/s GDDR interface [1]. However, the complexity of the transmitter and the CIO, capacitance of I/O, increase due to additional equalizers and pre- and de-emphasis drivers. For a compact transmitter, a low-overhead boosted transmitter is developed [4]. This paper presents an adaptive-bandwidth PLL in response to the supply and channel noises, a fast pre-charged data sampler without an additional decision-feedback equalizer (DFE), a crosstalk-induced-jitter-reduction technique and a compact transmitter with pre- and de-emphasis.

An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator

An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10-12 at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm2 using 0.13μm CMOS process.