Minyoung Song

A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection

This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm2 and 0.94 mm2, respectively, in a 0.13 μm 1P8M CMOS process.

A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile

A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH ΔΣ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of ±0.5% to 3.5% in steps of 0.5% and three modulation frequencies of fm, 2 fm and 3 fm. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 mm2 in a 0.13-μm CMOS process and consuming 23.72 mW at 3.5 GHz.

A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13- μm CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm2 consumes 12 mA and its measured jitter is 4 psrms at 2.4 GHz.

Acid Treatments of Carbon Nanotubes and Their Application as Pt-Ru/CNT Anode Catalysts for Proton Exchange Membrane Fuel Cell

Different oxidation treatments on CNTs using diluted 4.0 M H2SO4 solution at room temperature and or at 90oC reflux nconditions were investigated to elucidate the physical and chemical changes occurring on the treated CNTs, which might have nsignificant effects on their performance as catalyst supports in PEM fuel cells. Raman spectroscopy, X-ray diffraction and ntransmission electron microscope analyses were made for the acid treated CNTs to determine the particle size and distribution nof the CNT-supported Pt-Ru nanoparticles. These CNT-supported Pt-based nanoparticles were then employed as anode ncatalysts in PEMFC to investigate their catalytic activity and single-cell performance towards H2 oxidation. Based on PEMFC nperformance results, refluxed Pt-Ru/CNT catalysts prepared using CNTs treated at 90oC for 0.5 h as anode have shown better ncatalytic activity and PEMFC polarization performance than those of the commercially available Pt-Ru/C catalyst from ETEK nand other Pt-Ru/CNT catalysts developed using raw CNT, thus demonstrating the importance of acid treatment in nimproving and optimizing the surface properties of catalyst support.

A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC

An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65nm CMOS process burns 17mW and occupies 0.4mm2. The measured jitters are 1.1nspp and 223.6psrms, respectively with a multiplication factor of 1,024.

Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation

We propose a novel modulation profile for a spread spectrum clock generator (SSCG). The proposed piecewise linear (PWL) modulation profile significantly reduces electromagnetic interference with a simple implementation. Two SSCGs with two- and three-slope-PWL modulation profiles are used. Both SSCGs consist of the proposed spread spectrum control profile generator and a phase-locked loop that includes a high-resolution fractional divider to reduce quantization noise from a delta-sigma modulator. The SSCG with the two-slope-PWL modulation profile was fabricated in a 0.18 μm 1P4M CMOS technology. The measured peak power reduction level of the two-slope-PWL modulation profile is 14.2 dB with 5000 ppm down spreading at 1.5 GHz. The SSCG occupies an active area of 0.49 mm2 and consumes 40 mW of power at 1.5 GHz. The SSCG with the three-slope-PWL modulation profile was fabricated in a 0.13 μm 1P6M CMOS technology. The measured peak power reduction level of the three-slope-PWL modulation profile is 10.3 and 10.52 dB with 5000 ppm down spreading at 162 and 270 MHz, respectively. The SSCG occupies an active area of 0.096 mm2 and dissipates 1 mW of power at 270 MHz.

A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation

A spread spectrum clock generator is implemented in a 0.18 mum CMOS process employing the proposed piecewise linear modulation profile to significantly reduce EMI with a simple implementation. A high resolution fractional divider to reduce quantization noise from the modulation is proposed as well. A peak power reduction level of 14.2 dB with 5000 ppm down spreading and 27.88 pspp of jitter in the SSCG without modulation are measured.

10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation

A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70 pspp, respectively, with a multiplication factor of 1024.

A cost-effective design of spread spectrum clock generator

This paper provides a tutorial review of spread spectrum clock generators (SSCG). After explaining the various EMI reduction techniques, SSCGs which reduce EMI with frequency modulation are presented. The frequency modulation method and its implementation are also introduced. A low-cost SSCG design method that does not sacrifice EMI reduction is presented. The paper concludes with future trends of SSCGs.

A 0.076mm 2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS

A spread-spectrum clock generator (SSCG) is a cost-effective solution to reduce EMI, which has become a serious problem in high-speed systems. In applications such as serial links, display drivers and consumer electronics, SSCG is essential or strongly recommended. Control options such as frequency deviation (δ) and modulation frequency (fm) help to satisfy these demands. Furthermore, efficient modulation-profile generation is critical for achieving further EMI reduction and lowering fabrication cost. PLL-based SSCGs are reported in [1–3]. The ΔΣ modulator (ΔΣM) controls the division ratio [1,2] and the phase information of phase detector (PD) [3] to generate a spread-spectrum clock. The self-referenced clock generator uses a capacitor array to generate a spread-spectrum clock [7]. However, they do not have a way to control δ and fm. Dual-loop direct VCO modulation [4] and digital period synthesizer with delay-line [5] are able to control δ and fm. However, [4] requires an additional VCO, which increases the power consumption by 2×, and [5] suffers from a large deterministic jitter through the delay-line and logic circuits. A triangular profile is commonly used in many SSCGs [1,3,4]. Though the implementation of a triangular profile is very simple, its performance is poor. The chaotic PAM modulation in [2] requires complex analog circuits. Recently, a piecewise-linear profile with SRAM was presented in [5]. However, the additional memory consumes a large amount of power and occupies a large area. This paper presents a frequency-locked loop (FLL) based SSCG with frequency-to-voltage converter (FVC) [6], that saves area and provides multiple δ with low bandwidth variation. A memoryless Newton-Raphson modulation profile with multiple fm is also described.