Shahram Karimi

FPGA-Based Real-Time Power Converter Failure Diagnosis for Wind Energy Conversion Systems

This paper discusses the design, implementation, experimental validation, and performances of a field-programmable gate array (FPGA)-based real-time power converter failure diagnosis for three-leg fault tolerant converter topologies used in wind energy conversion systems (WECSs). The developed approach minimizes the time interval between the fault occurrence and its diagnosis. We demonstrated the possibility to detect a faulty switch in less than 10 mus by using a diagnosis simultaneously based on a ldquotime criterionrdquo and a ldquovoltage criterion.rdquo To attain such a short detection time, an FPGA fully digital implementation is used. The performances of the proposed FPGA-based fault detection method are evaluated for a new fault tolerant back-to-back converter topology suited for WECS with doubly fed induction generator (DFIG). We examine the failure diagnosis method and the response of the WECS when one of the power switches of the fault tolerant back-to-back converter is faulty. The experimental failure diagnosis implementation based on ldquoFPGA in the looprdquo hardware prototyping verifies the performances of the fault tolerant WECS with DFIG.

Current Sensor Fault-Tolerant Control for WECS With DFIG

The performances of wind energy conversion systems (WECS) heavily depend on the accurate current sensing. A sudden failure in one of the current sensors decreases the system performances. Moreover, if a fault is not detected and handled quickly, its effect leads to system disconnection. Hence, to reduce the failure rate and to prevent unscheduled shutdown, a real-time fault detection, isolation, and compensation scheme could be adopted. This paper introduces a new field-programmable-gate-array (FPGA)-based grid-side-converter current sensor fault-tolerant control for WECS with doubly fed induction generator. The proposed current sensor fault detection is achieved by a predictive model. ldquoFPGA-in-the-looprdquo and experimental results validate the effectiveness and satisfactory performances of the proposed method.

An HIL-Based Reconfigurable Platform for Design, Implementation, and Verification of Electrical System Digital Controllers

This paper presents a top-down design flow for design, implementation, and verification of digital controllers associated with electrical systems. In the proposed design flow, the functional description of the studied system and the detailed electronic hardware design and validation of the digital controller are performed using a hardware-in-the-loop (HIL)-based reconfigurable platform in a unique design environment. The way of using this design flow and the reconfigurable HIL platform is analyzed through a fault-tolerant shunt active power filter application. The experimental results obtained with a laboratory prototype fault-tolerant active filter demonstrate the performances and the efficiency of the proposed design flow and HIL-based reconfigurable platform.

A Design Methodology for Power Electronics Digital Control based on an FPGA in the Loop Prototyping

This paper presents a methodology to design and prototype an FPGA-based fully digital controller for power electronics systems. A Top-down methodology is used to study step by step the digital adaptation and implementation of the control algorithm. Finally, an experimental FPGA in the loop prototype is achieved, based on MATLAB/SimPower Systems and Altera DSP Builder mixed simulation tools. Modeling, mixed simulation and FPGA in the loop prototyping are achieved in a unique design environment. An application using the proposed methodology is studied: a fully digital controller for a single- phase parallel active power filter. The controller is described and the control algorithm examined with FPGA in the loop prototyping.

FPGA-based hardware in the loop validation for fault tolerant three-phase active filter

This paper proposes a new robust fast power switch fault detection and compensation for a three phase shunt active filter without redundant leg. The approach introduced in this paper minimizes the time interval between the fault occurrences and its diagnosis. This paper demonstrates the possibility to detect a faulty switch of the active filter in less than 10 mus by using simultaneously a ldquotime criterionrdquo and a ldquovoltage criterionrdquo without false fault detection due to power semiconductors switching. In order to attain this short detection time a FPGA (field programmable gate array) is used. After fault detection, the classical three-leg shunt active filter is reconfigured in a two-leg topology. In this case the faulty phase is connected to the middle point of the DC bus. The studied fault detection method is implemented using a FPGA and experimentally validated. The experimental results based on ldquoFPGA in the looprdquo hardware prototyping show good agreement with theoretically analyses.

Reference current generation without PLL for shunt active filter under distorted and unbalanced conditions

The performances of an active power filter depends on many factors, but mainly on the selected reference generation strategy. This paper proposes a new high performances selective band pass filter (SBPF) to extract the fundamental component directly from electrical signals (voltage and current) in alpha-beta reference frame. The major advantages of the proposed SBPF are the following: 1) operating adequately in steady state and transient condition; 2) no phase delay and unity gain at the fundamental frequency; 3) suppression of the negative sequence components; 4) no PLL is required; 5) easy implementation in digital and analogue control system. In this paper the frequency and dynamic response of the SBPF are mathematically analyzed and discussed. More, we propose a modified version of the PQ theory based on SBPF to generate current references for harmonic compensation and mains current balancing. Experimental results by ldquoFPGA in the looprdquo prototyping validate the effectiveness of the proposed reference currents generation strategy in distorted and/or unbalanced conditions.

Design methodology of VLSI power electronics digital controller based on Matlab-Modelsim co-simulation

This paper presents a methodology to design Very Large Scale Integration (VLSI) fully digital controller for power electronics. Step by step, the proposed top-down methodology based on very high speed integrated circuits Hardware Description Language (VHDL) and on Matlab-Modelsim co-simulation is presented. It is used to study and validate the digital adaptation and the architecture implementation of the control algorithm. Modelling, Matlab-Modelsim co-simulation and virtual prototyping are achieved in a unique design environment managed by Matlab computer aided design tools. An application using the proposed methodology was studied: a digital controller for three-phase Shunt Active Power Filter (SAPF). The power circuit has been modelled in the Matlab/Simulink environment, using the dedicated Power System Blockset (PSB) toolbox. The digital controller is modelled in VHDL code in the Modelsim environment. Then, this VHDL model is imported into Matlab environment and co-simulated using the Link-for-Modelsim toolbox. A high level VHDL model for the controller using real data format has been first designed and validated by co-simulation. Then, an optimized VLSI architecture for the controller using a specific data binary format has been modelled in VHDL code at Register Transfert Level and successfully validated by Matlab-Modelsim co-simulation.

FPGA-based real time current sensor failure diagnosis for shunt active power filters

The performances of conventional shunt active power filters heavily depend on accurate active filter current sensing. A sudden failure in one of the active filter current sensors decreases the filter performances. Moreover, if the fault is not detected and compensated for quickly, its effect leads to disconnection or hard failure of the active filter. Hence, to reduce the failure rate and to prevent unscheduled shutdown, a real-time fault detection, isolation and compensation scheme could be adopted. This article introduces a new fast and robust current sensor fault detection and compensation method for three-phase shunt active power filters. The proposed current sensor fault detection is achieved with a predictive model associated with a logical decision. The satisfactory performances obtained by experimental ‘FPGA in the loop’ prototyping validate the effectiveness of the proposed method.

Current sensors and power switches fault detection and compensation for shunt active power filters

This paper presents current sensors and power switches fault detection and compensation for shunt active power filters. Active filter topology is based on a redundant fault tolerant four-leg structure. Power switches fault detection is based on a new fast and reliable detection method. Current sensors fault is achieved by a direct current estimator associated with a logical decision. Simulation results demonstrate the effectiveness of detection, isolation and reconfiguration performances in fault cases of current sensors or switches.