Shanggar Periaman

A novel inter-package connection for advanced package-on-package enabling

This paper presents a novel enabling technique exploiting interposer approach such as silicon and package interposer in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution. The electrical performance of such interconnect innovation is discussed in this paper, and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. This paper also highlights the advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses, of which modeling and simulation data are presented. Other attributes e.g. device input-output (IO) density and physical scalability associated with the above inter-package connection systems are also compared and further elaborated in this paper.

Capillary underfill and mold encapsulation materials for exposed die flip chip molded matrix array package with thin substrate

This paper discusses the work on capillary underfill and mold technology to assemble exposed die backside Flip Chip Molded Matrix Array. Parts were successfully assembled and subjected to reliability stress test. The interaction between capillary underfill and mold compound materials are crucial for assembly and reliability performances of this configuration. Both materials need to be chemically and physically compatible to achieve high reliability performance.

Signal integrity and scalability study of a novel PoP inter-package system

A novel enabling technique exploiting interposer approach such as silicon and package interposer [1] in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution is presented in this paper. Electrical performance of such interconnect innovation is discussed and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. The advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses are presented based on 3D passive modeling and simulation data. Device input-output (IO) density and physical scalability as associated with the above inter-package connection systems are also being analyzed and further elaborated. Transient analysis in terms of impulse response and TDR are presented in this paper as well.

Signal integrity study of high density through silicon via (TSV) technology

This paper explores the electrical performance of several multi-channel TSV designs i.e. cross-etched full-plated TSV and cross-etched partial-plated TSV to further improve data transmission bandwidth among the vertically stacked silicon devices. The electrical characteristics of the multi-channel TSV designs were investigated and compared against the conventional TSV design in terms of return loss, insertion loss, near-end (NEXT) and far-end (FEXT) crosstalk. Fullwave electromagnetic simulation data showed the insertion loss performance of the multi-channel TSV designs are at par with the conventional TSV design up-to 50GHz. Meanwhile, the multi-channel TSV designs were found yielding improved NEXT and FEXT crosstalk performance. Transient analyses of respective TSV designs are also included in this paper for more conclusive discussions.