Bok Eng Cheah

Signaling analysis of inter-chip I/O package routing for Multi-Chip Package

Multi-Chip Package (MCP) is becoming a customary form of integration in many high performance and advanced electronic devices. The vast adoptions of this technology are mainly contributed by advantages for instance lower power consumption, heterogeneous integration of multiple silicon process technologies and manufacturers, shorter time-to-market and lower costs [1]. However, the high density interchip I/O routing within package presents unique signaling challenges when coupled with high operating data rate. This paper focuses on the signaling analysis of the inter-chip I/O package routing between silicon devices in MCP. In this study, high level signal quality and eye margin sensitivity were evaluated from 2.5GHz up-to 7.5GHz. The microwave effect is found dominating the transmission line component that resulted in signal quality deteriorations. Key limiting factors such as crosstalk coupling effects, signal reflections and frequency dependent losses that caused signal quality degradations were identified and categorized according to the operating frequency and channel length for future MCP design considerations.

A novel inter-package connection for advanced package-on-package enabling

This paper presents a novel enabling technique exploiting interposer approach such as silicon and package interposer in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution. The electrical performance of such interconnect innovation is discussed in this paper, and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. This paper also highlights the advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses, of which modeling and simulation data are presented. Other attributes e.g. device input-output (IO) density and physical scalability associated with the above inter-package connection systems are also compared and further elaborated in this paper.

Intrinsic capacitance extraction and estimation for system-on-chip power delivery development

This paper presents the methodology of on-die parasitic intrinsic capacitance extraction and estimation at the early phase of system-on-chip (SOC) design and development cycle. Accurate estimation of the intrinsic capacitance is critical to prevent circuit overdesign and additional on-die decoupling capacitance requirements that could result in larger silicon footprint. The correlation of the simulated results and silicon measurement data is presented and further discussed in this study. Impacts of intrinsic capacitance to the power delivery capacitance and overall intellectual property (IP) block design optimization are also enveloped in this paper.

Signal integrity and scalability study of a novel PoP inter-package system

A novel enabling technique exploiting interposer approach such as silicon and package interposer [1] in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution is presented in this paper. Electrical performance of such interconnect innovation is discussed and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. The advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses are presented based on 3D passive modeling and simulation data. Device input-output (IO) density and physical scalability as associated with the above inter-package connection systems are also being analyzed and further elaborated. Transient analysis in terms of impulse response and TDR are presented in this paper as well.

Crosstalk study of high speed on-package interconnects for multi-chip package

This paper presents the crosstalk analysis study for high-speed on-package interconnects in multi-chip package (MCP). The crosstalk coupling effects from adjacent aggressors on signaling performance e.g. eye opening and signal overshoot were investigated in this study. Simulations were performed on both microstrip and stripline structures from 2Gbps up-to 6Gbps. Several key design parameters e.g. package trace width and trace spacing ratio as well as the channel length were further explored to identify the dominating factor of crosstalk coupling in the high-speed on-package interconnect design. Simulation results indicated the crosstalk effects from adjacent aggressors beyond second order still have significant impacts on the signaling performance and need to be carefully considered for high-speed MCP applications. This paper also establishes several guidelines to enable optimum design trade-off between signaling performance and silicon real-estate.

Package technology evaluation and optimization for high-speed applications

This paper analyzes the electrical performance of standard and coreless packages up-to 100Gbps data rate. The impact of package design attributes e.g. substrate core thickness, plated through hole (PTH) pad dimension and geometry of second level interconnect (SLI) on insertion loss performance are explored in this study. This study also evaluates the electrical performance of an alternative coreless package solution with metal grid array (MGA) SLI to enable ultra-thin and small form factor electronic devices. In addition to the advantages of configurable and scalable SLI geometry, the full-wave electromagnetic simulation results shows significant insertion loss performance improvement with MGA coreless package as the frequency increases. The root-causes of insertion loss degradations among the evaluated packaging solutions were identified and further discussed in this paper.

A novel trench routing for next-generation high-speed serial buses beyond 10Gbps applications

This work describes an innovative low-loss transmission line routing configuration, which enables improved channel margin in next-generation high-speed serial buses beyond 10Gbps applications. One such example is SuperSpeed Plus USB a.k.a. USB 3.1 Gen2. Ultimately, this novel routing when implemented in either substrate or printed circuit board (PCB) will extend platform length within the interconnect channel loss budget as stipulated by standard development body e.g. USB-IF specifications. This inventive routing provides huge benefit to original equipment manufacturer (OEM) in term of platform component removal (e.g. USB 3.1 re-timer that costs ∼

3D Interconnects — The enabler of next generation multi-Gbps single-ended bus

1) for high-speed differential links >10Gbps data transfer rates. These cost-adding repeaters would be indispensable under conventional routing for instance microstrip, stripline and dual-stripline for high-speed applications. The PCB trench routing aims to mitigate the existing and future challenges of next-gen multi-Gbps signaling, of which one of the platform length limitations is PCB interconnect loss. In this work, signaling analysis in 10Gbps USB 3.1 and 32Gbps SerDes applications have shown feasibility of yielding significant eye margin improvements i.e. up-to 30% voltage margin improvements, which also translates into ample board design flexibility with extended platform routing length.

Study of dielectric material property impact on insertion loss for advanced packaging solutions

The rising demands of miniaturize and high performance electronic gadgets necessitates higher density with higher bandwidth interconnect which is being limited by prevailing microwave effects as signaling data-rate surges and routing pitch shrinks. This paper presents a transmission line design with three-dimentional (3D) reference plane to alleviate the signaling crosstalk impacts that limit the performance scaling of high-speed parallel bus design such as on-package interconnects (OPI). Simulation result indicates eye opening improvements of >40% for OPI bus operates at 4Gbps data rate is feasibible with the crosstalk reduction achieved through the 3D reference plane design.

Study of conductor surface roughness impact on package insertion loss

This paper evaluates the impact of dielectric loss tangent property on electrical insertion loss performance for both conventional and coreless packaging designs up-to 100Gbps datarate. Coreless package with metal grid array (MGA) second level interconnect (SLI) that yields minimal impedance discontinuities was observed gaining more than 50% insertion loss improvements i.e. ~20% higher compared to conventional design with dielectric loss tangent improved from 0.03 to 0.006.