Jackson Chung Peng Kong

Efficiency Evaluation of Full-Wave Electromagnetic Simulation Techniques in 3D WB-PBGA Package Modeling

Package modeling and simulation is the essence of every designer daily work flow. With a trend towards ever more complex designs, the potential reward for designer is the ability to solve previously intractable problems quickly and accurately. Experts still argue about the fastest and most elegant approaches to solving electromagnetic problems yet no single method has emerged as an outright winner [1]. This paper presents a case study to make comparison between two enormously commercially-used full-wave electromagnetic (EM) simulation techniques in the advanced packaging technology. It examines the efficiency in terms of simulation time and memory requirement when modeling and simulating a 3D WB-PBGA package. Simulation results in both frequency and time domains have been obtained and correlated with empirical data.

A novel inter-package connection for advanced package-on-package enabling

This paper presents a novel enabling technique exploiting interposer approach such as silicon and package interposer in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution. The electrical performance of such interconnect innovation is discussed in this paper, and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. This paper also highlights the advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses, of which modeling and simulation data are presented. Other attributes e.g. device input-output (IO) density and physical scalability associated with the above inter-package connection systems are also compared and further elaborated in this paper.

Impact on signal integrity of differential pair routing over split plane and voids

Differential pair routing on Printed Circuit Board (PCB) level is widely used as interconnection due to its excellent performance in signal integrity. However, differential pair routing is not perfectly immune to the impact of routing discontinuities. This paper analyzes the impact of differential pair microstrip with routing discontinuities by using industrial configuration standard. There are two types of routing discontinuities that are discussed in this paper. They are routing over split plane and routing over void. The results of this research are based on Ansoft HFSS fullwave 3D modeling and analysis simulation. The simulation results consist of three parts which are S-parameter, TDR and full channel transient analysis. The transmission line cross-sectional is based on SATA3 industrial geometry design. From this research, the results show that the impact of differential pair routing with routing discontinuities is significant, in view of signal integrity performance degradation.

Signal integrity and scalability study of a novel PoP inter-package system

A novel enabling technique exploiting interposer approach such as silicon and package interposer [1] in the area of package-on-package (PoP) technology to achieve ultra small form factor packaging solution is presented in this paper. Electrical performance of such interconnect innovation is discussed and pitted against the conventional PoP methods using solder ball connection, as well as the recent developed over-molded interconnection technology. The advantages of the aforementioned silicon and package interposer technology from electrical performance perspective such as signal integrity in terms of impedance matching, noise shielding, electrical return and insertion losses are presented based on 3D passive modeling and simulation data. Device input-output (IO) density and physical scalability as associated with the above inter-package connection systems are also being analyzed and further elaborated. Transient analysis in terms of impulse response and TDR are presented in this paper as well.

Crosstalk study of high speed on-package interconnects for multi-chip package

This paper presents the crosstalk analysis study for high-speed on-package interconnects in multi-chip package (MCP). The crosstalk coupling effects from adjacent aggressors on signaling performance e.g. eye opening and signal overshoot were investigated in this study. Simulations were performed on both microstrip and stripline structures from 2Gbps up-to 6Gbps. Several key design parameters e.g. package trace width and trace spacing ratio as well as the channel length were further explored to identify the dominating factor of crosstalk coupling in the high-speed on-package interconnect design. Simulation results indicated the crosstalk effects from adjacent aggressors beyond second order still have significant impacts on the signaling performance and need to be carefully considered for high-speed MCP applications. This paper also establishes several guidelines to enable optimum design trade-off between signaling performance and silicon real-estate.

A novel trench routing for next-generation high-speed serial buses beyond 10Gbps applications

This work describes an innovative low-loss transmission line routing configuration, which enables improved channel margin in next-generation high-speed serial buses beyond 10Gbps applications. One such example is SuperSpeed Plus USB a.k.a. USB 3.1 Gen2. Ultimately, this novel routing when implemented in either substrate or printed circuit board (PCB) will extend platform length within the interconnect channel loss budget as stipulated by standard development body e.g. USB-IF specifications. This inventive routing provides huge benefit to original equipment manufacturer (OEM) in term of platform component removal (e.g. USB 3.1 re-timer that costs ∼

3D Interconnects — The enabler of next generation multi-Gbps single-ended bus

1) for high-speed differential links >10Gbps data transfer rates. These cost-adding repeaters would be indispensable under conventional routing for instance microstrip, stripline and dual-stripline for high-speed applications. The PCB trench routing aims to mitigate the existing and future challenges of next-gen multi-Gbps signaling, of which one of the platform length limitations is PCB interconnect loss. In this work, signaling analysis in 10Gbps USB 3.1 and 32Gbps SerDes applications have shown feasibility of yielding significant eye margin improvements i.e. up-to 30% voltage margin improvements, which also translates into ample board design flexibility with extended platform routing length.

Study of dielectric material property impact on insertion loss for advanced packaging solutions

The rising demands of miniaturize and high performance electronic gadgets necessitates higher density with higher bandwidth interconnect which is being limited by prevailing microwave effects as signaling data-rate surges and routing pitch shrinks. This paper presents a transmission line design with three-dimentional (3D) reference plane to alleviate the signaling crosstalk impacts that limit the performance scaling of high-speed parallel bus design such as on-package interconnects (OPI). Simulation result indicates eye opening improvements of >40% for OPI bus operates at 4Gbps data rate is feasibible with the crosstalk reduction achieved through the 3D reference plane design.

Method to improve ball grid array Imax distribution for small form factor package design

This paper evaluates the impact of dielectric loss tangent property on electrical insertion loss performance for both conventional and coreless packaging designs up-to 100Gbps datarate. Coreless package with metal grid array (MGA) second level interconnect (SLI) that yields minimal impedance discontinuities was observed gaining more than 50% insertion loss improvements i.e. ~20% higher compared to conventional design with dielectric loss tangent improved from 0.03 to 0.006.

Capacitive crosstalk compensation structure for improved high-speed on-package signaling

Maximum current (Imax) distribution across substrate has been one of the major design factors that govern the electronic package form factor. Particularly on ball grid array (BGA) package design, often times Imax distribution determines the number of solder balls required for each interface to sustain respective workloads hence defines the total ball count and the x-y dimension of the electronic package. This paper introduces a new method to improve BGA Imax distribution while keeping ball count minimal for to enable small form-factor package design. The proposed solution utilizes fundamental of electrical resistance control through on-board BGA pad design customization to achieve more uniform Imax distribution across solder balls and enable up-to 25% Imax reduction with negligible IR drop impact. Power losses across plane were also simulated and compared against conventional design in this study.