Tonse Laxminidhi

Widely Programmable High-Frequency Active RC Filters in CMOS Technology

We propose a circuit technique that enables the realization of widely programmable high-frequency active RC filters in CMOS technology. A fifth-order Chebyshev ladder filter having a digitally programmable 3-dB bandwidth (from 44 to 300 MHz) is used as a vehicle to validate our ideas. The opamp uses feedforward compensation for achieving high dc gain and wide bandwidth. The integrating resistors are realized as a series combination of a triode-operated MOSFET and a fixed polysilicon resistor. A charge-pump-based servo loop servoes the integrating resistor to a stable off-chip resistor. The principle of ldquoconstant capacitance scalingrdquo is applied to the opamp and the integrating resistors so that the shape of the frequency response is maintained when the bandwidth is scaled over a 7 times range. The filter core, designed in a 0.18-mum CMOS process, consumes 54 mW from 1.8-V supply and has a dynamic range of 56.6 dB.

Low power fully differential, feed-forward compensated bulk driven OTA

A low voltage, low power bulk driven Operational Transconductance Amplifier (OTA) is designed in 180 nm CMOS Technology. The OTA employs feed-forward compensation achieving open loop DC gain of 44.05 dB, 3 dB bandwidth of 408 kHz, Unity Gain Bandwidth (UGB) of 9.07 MHz. OTA is stable with phase margin of 45° and a gain margin of 66 dB for a pure capacitive load of 1 pF. OTA operates on 0.5 V supply consuming a power of 30 µW.

A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC

This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18μm technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V.

Common Mode Feedback Circuits for Low Voltage Fully-Differential Amplifiers

Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5V in 0.18μm standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1fF to tens of femto farads.

LOW VOLTAGE, LOW POWER CHEBYSHEV FILTER IN 0.18 μm CMOS TECHNOLOGY

This paper presents an active-RC continuous time filter in 0.18 μm standard CMOS technology intended to operate on a very low supply voltage of 0.5 V. The filter designed, has a 5th order Chebyshev low pass response with a bandwidth of 477 kHz and 1-dB passband ripple. A low-power operational transconductance amplifier (OTA) is designed which makes the filter realizable. The OTA uses bulk-driven input transistors and feed-forward compensation in order to increase the Dynamic Range and Unity Gain Bandwidth, respectively. The paper also presents an equivalent circuit of the OTA and explains how the filter can be modeled using descriptor state-space equations which will be used for design centering the filter in the presence of parasitics. The designed filter offers a dynamic range of 51.3 dB while consuming a power of 237 μW.

0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS Process

In this paper a low power continuous-time 4th order low pass Butterworth filter operating at power supply of 0.5 V is presented. A 3-dB bandwidth of 1 MHz using technology node of 0.18 μm is achieved. In order to achieve necessary head-room, the filter uses pseudo-differential bulk-driven transconductor. A master-slave based common mode feedback(CMFB) circuit sets the output common mode voltage of transconductor. The simulation results show that the filter has a dynamic range of 54 dB and consumes a total power of 36 μW when operating at a supply voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ, lowest among similar low-voltage filters found in the literature. The simulation result show that the 3-dB bandwidth variation for process, voltage and temperature is less than ±10%.

0.5 V, 3 6µW G m -C Butterworth low pass filter in 0.18µm CMOS process

This paper presents a low voltage, low power continuous-time (Gm-C) 4th order low pass Butterworth filter with a 3-dB bandwidth of 1MHz and capable of operating at supply voltage as low as 0.5V in 0.18 μm. The filter uses bulk-driven technique for achieving the necessary head-room. The simulation results show that the filter has a peak-to-peak signal swing of 1.2V (differential) for 1% THD and a dynamic range of 54 dB. The power consumed by the filter is 36μW when operating at a voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ and is found to be lowest among the similar filters found in the literature.

LOW POWER CONTINUOUS TIME COMMON MODE SENSING FOR COMMON MODE FEEDBACK CIRCUITS

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

A 1.8 V 8.62 µW Inverter-based Gain-boosted OTA with 109.3 dB dc Gain for SC Circuits

ABSTRACT This paper presents a low-power inverter-based gain-boosted operational transconductance amplifier (OTA) for switched capacitor (SC) circuits operating at higher supply voltage (>1 V). The proposed OTA is implemented using UMC 180 nm CMOS technology with a supply voltage of 1.8 V and it offers a high dc gain with a unity gain bandwidth (UGB) suitable for audio applications. All the transistors of the proposed OTA are operated in sub-threshold region to minimize the power consumption. Gain-boosting technique is employed to achieve a higher dc gain. The post-layout simulations demonstrate the robust performance of the proposed OTA, which delivers a high dc gain of 109.3 dB and a UGB of 5.29 MHz at 81° phase margin (PM) with a capacitive load of 2.5 pF for a typical process corner at room temperature (27°C). The proposed OTA draws a quiescent current ( ) of 4.79 µA, resulting in a power consumption of 8.62 µW.

A Gyrator Based Output Resistance Enhancement Scheme for a Differential Amplifier

This paper proposes a scheme to enhance the output resistance of a differential amplifier. A gyrator based loop is used to offer a negative resistance to cancel the output resistance of the differential amplifier. The proposed scheme can give an enhancement of about three folds (in dB) in the DC gain of the basic differential Tran conductor, without loss in linearity. The concept has been validated using a Tran conductor designed in UMC 180 nm CMOS process. The results show an enhancement of 72 dB over 22 dB gain of the basic Tran conductor. A two stage OTA designed using this scheme is found to offer least sensitivity of gain boost over output voltage swing across process corners, at nominal voltage and temperature, when compared to other methods found in literature.