Shao-Chang Huang

Power-Tracking Embedded Buck–Boost Converter With Fast Dynamic Voltage Scaling for the SoC System

A power-tracking embedded buck-boost converter with a fast dynamic voltage scaling (F-DVS) function is proposed to power the system-on-a-chip (SoC) system. To meet the power request of the SoC for different operation functions, fast up/down-tracking is implemented to achieve the F-DVS function. Recycling energy is also derived to minimize power dissipation during the down-tracking period. In addition, the peak current control and valley current control methods are utilized in the buck and boost operations, respectively, to minimize the effect of switching noise in high switching operation for compact solution. Moreover, the self-tuning pulse skipping mechanism extends the effective duty cycle to achieve voltage regulation and improves efficiency when the input voltage is close to that of the output. Through F-DVS, the tracking speed from 3 to 2 V and vice versa are 15 and 20 μs, respectively, with a high switching frequency of 5 MHz.

Fast Transient (FT) Technique With Adaptive Phase Margin (APM) for Current Mode DC-DC Buck Converters

This paper proposes a fast transient (FT) control with the adaptive phase margin (APM) to achieve good transient response in current-mode DC-DC buck converters at different load conditions. The overshoot/undershoot voltage and the transient recovery time are effectively reduced. The APM control can always maintain the system phase margin at an adequate value under different load conditions. That is, the compensation pole-zero pair is adapted to load current to extend the system bandwidth and get an adequate phase margin. Experimental results show the overshoot/undershoot voltage is smaller than 60 mV (3%) and transient period is smaller than 12 μs as load current suddenly changes from 100 to 500 mA, or vice versa. Compared with conventional designs without any fast transient technique, the undershoot voltage and recovery time are enhanced by 45% and 85%, respectively.

Semiself-Protection Scheme for Gigahertz High-Frequency Output ESD Protection

In this paper, a semiself-protection scheme is proposed and developed for gigahertz output electrostatic-discharge (ESD) protection. The output transistor acts as a trigger device to trigger the ESD protection device, and then, it is turned off when the ESD protection device turns on. Thus, the capacitance of a gigahertz high-frequency output pad can be minimized because this scheme is without any additional trigger device or any passive component.

Two-stage trigger silicon-controller rectifier (SCR) for radio-frequency (RF) ESD protection in the nanometer technologies

In this paper, a two-stage trigger (TST) scheme is proposed to implement a low-capacitance and zero-ohm input resistance electrostatic-discharge (ESD) protection device for nanometer technologies. This scheme includes two different kinds of trigger devices. The diode string is the first trigger device, which provides the substrate current to trigger the output transistor on. As the output transistor is turned on, the source begins to inject the electrons. Thus, some of the electrons are collected to the anode of the silicon-controller rectifier (SCR) for driving it into the latch-up state. With the additional trigger device, the dimension of the main trigger device can be reduced to minimize its capacitance. Moreover, the output transistor can connect to the pad directly without any resistor since the diode string can be turned on before the output transistor is turned on.

Embedded I/O PAD Circuit Design for OTP Memory Power-Switch Functionality

An additional high-voltage pad is generally applied for one-time-programming (OTP) memory product applications. This may increase the complexity of input/output (I/O) pad arrangement and the area penalty. In this paper, a novel approach of I/O circuit embedded with the power-switch function is proposed for multifunction integrations in one I/O pad. The capabilities of high-voltage programming, I/O signal handling, electrostatic discharge protection and latch-up prevention for this novel circuit are well examined from silicon verifications.