Yi-Hsun Wu

A Simple and Useful Layout Scheme to Achieve Uniform Current Distribution for Multi-Finger Silicided Grounded-Gate NMOS

The influence of the contact-to-contact space on the ESD performance of multi-finger silicided ground-gate NMOS (GGNMOS) is investigated. We find that the conventional contact layout, which has short contact-to-contact space, induces current localization, and degrade the device ESD performance. Here we discuss how to design a ballast resistor for silicided multi-finger GGNMOS and show that lengthening the contact spacing can significantly improve device ESD performance (It2, HBM and MM). This improvement eliminates the short channel induced degradation of thin oxide device ESD

An analytical model of positive HBM ESD current distribution and the modified multi-finger protection structure

In order to study the ESD zapping current distribution variation with the well pick-up layout, a new transmission-line equivalent-circuit model is proposed which includes the effects of parasitic bipolar transistors and the horizontal and vertical P-well resistance. Based on this equivalent circuit and from real-time I-V characteristics during ESD zapping (Duvvury and Diaz, 1992), an analytical solution can be derived. For conventional multi-finger structures, it shows that the maximum current or power density of the device under the ESD zapping event is located at the region near the P-well pick-up. This model prediction is consistent with the devices damage sites after ESD zapping. Based on this model, a novel protection structure leading to uniform current distribution can be achieved by inserting P/sup +/ diffusion into each source region of NMOS devices. From the real-time I-V characteristics during ESD zapping, a new phenomenon termed the self-biasing effect is also observed. In order to sustain sufficient substrate potential to keep the bipolar turn-on, the devices snapback voltage should increase to generate more impact ionization current when the effective substrate resistance decreases. We observed the phenomenon that snapback voltage is varied with the device layout. As a result, higher snapback voltage may not lead to lower ESD threshold voltage.

High current characteristics of copper interconnect under transmission-line pulse (TLP) stress and ESD zapping

The Cu metal interconnect under TLP stress can not be treated as the constant current stress. The increase in the metal interconnect length at GGNMOS drain can improve devices MM failure threshold but degrade devices HBM failure threshold and IT2.

A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O

The gate voltage-induced current crowding (GVICC) effect (Lee, J.H., et al., IRPS Proc., p.269-76, 2003) has been found to be the root cause of the failure of the high voltage tolerant I/O (HVT I/O) at a low-voltage ESD event. Based on this finding, a new pre-driver design is proposed to pull down the voltages of the top gate and the bottom gate of the cascode NMOS to 0 V during an ESD zapping event in order to eliminate the GVICC effect. The new pre-driver design can improve the ESD performance of the fully silicided HVT I/O from 500 V to 5 kV during HBM ESD zapping.

Comparison of ultra-thin gate oxide ESD protection capability of silicided and silicide-blocked MOSFETS

In this paper, ultra-thin oxide ESD protection capability of silicided and silicide-blocked MOSFETs is studied. We find that ground Gate NMOSFETs (GGNMOS) with silicided drain can provide much better ultra-thin oxide ESD protection capability than the GGNMOS with silicide-blocked drain, and oxide damage is occurred at the transient before the device occurring the snapback. Because the device under the TLP and ESD has different discharge behaviors at the transient before the snapback, it results in that TLP test result does not correlate to ESD test result.

The Mechanism Responsible for a Low Electrostatic Discharge Failure Threshold of an Output Buffer Circuit with Low Current Drive Capability

The electrostatic discharge (ESD) failure threshold of an output buffer is observed to be sensitive to the used-gate finger number. It is found that the lower the current drive capability, the lower the ESD failure threshold, and the damage sites of the output buffer are always located at the used gate n-channel metal-oxide semiconductor (NMOS) transistors. This observation can only be explained on the basis of the energy dissipation (E=VSP×ID×time) in each finger, where ID is composed of channel current and bipolar current. From the real-time current-voltage measurement during ESD zapping, three phenomena are observed. The first is that a transistor with a floating gate (used-gate fingers) has a larger snapback voltage (VSP) than that with a grounded gate transistor. The second is that due to the accumulation of hot holes in the floating gate, a constant gate voltage can be induced during the ESD zapping. The last is that this induced-gate-voltage can assist the switching on of the NMOS transistors and reduction of the ESD duration. Therefore, the ESD duration of a transistor with high current drive capability will be much shorter than that of low current drive capability. As a result, high current drive capability leads to a high ESD failure threshold.