Shaoqing Li

Multiple-precision subword-parallel multiplier using correction-value merging technique

This paper presents a 64-bit subword-parallel multiplier capable of supporting multiple precisions. The proposed multiplier uses novel correction-value merging technique to perform one 64times64, two 32times32 or four 16times16 bit unsigned/signed multiplication operations in parallel. The multiplier is implemented in 0.18 mum CMOS process. Critical path delay is 2.88 ns and layout area is 1.65 mm2, which are comparable to conventional multipliers.

A 2.5-Gb/s 0.13-μm CMOS current mode logic transceiver with pre-emphasis and equalization

A 2.5-Gb/s current-mode logic (CML) transceiver is implemented in 0.13 - mum CMOS technology for serial inter-chip interconnection. To compensate the channel attenuation and other impairments, pre-emphasis circuit is included at the transmitter and equalizer at the receiver. 6-GHz 3 dB bandwidth is achieved through the use of active inductors instead of online spiral inductors. DC offset compensate circuits are employed in the output and input buffers to keep the common mode voltage stable. Layout simulation demonstrates the effectiveness of the transceiver. This transceiver consumes only 160 mw of power with 2.5v power supply. The die area of transmitter and receiver are 0.015 mm2, 0.01 mm2 respectively. The transceiver can be operated at 2.5-Gb/s with 100 mv receiver sensitivity.

A Look-Up-Table Based Differential Logic to counteract DPA attacks

Dual-Rail Precharge (DRP) logic styles, such as Wave Dynamic Differential Logic (WDDL), have been proposed as a countermeasure against Differential Power Analysis (DPA) for years. Because of the constant transition rate, the correlation between power consumption and signal values is significantly reduced. However, leakage still occurs in these logic styles caused by the difference of signal delay time. In this paper, a novel Look-Up-Table (LUT) Based Differential Logic (LBDL) is presented. The transition time of LBDL gates are independent of input values, hence the power consumption of LBDL is constant though the signals have different delays. Experimental results indicate that LBDL eliminates most of the leakage, while the performance and area costs are similar to WDDL1.

Cost effective soft error mitigation for parallel adders by exploiting inherent redundancy

Soft errors in combinational logic have been considered as an important challenge for VLSI circuit design. As a kind of representative element of combinational logic, adders are widely used in arithmetic units. This paper presents a cost effective soft error mitigation technique for high speed parallel adders. By exploiting inherent hardware redundancy and temporal redundancy of circuit, this technique greatly reduces area overhead and delay overhead of fault tolerance. We also combine C-element-based error correction techniques with inherent hardware and temporal redundancy to enhance error correction capability of adders. In addition, we propose a new metric ADP to evaluate global overheads of soft error mitigation. Experiments show that the proposed technique can correct 93.76% of soft errors only with 12.23% of area and 6.41% of delay overhead. The proposed adder has the least ADP and best tradeoff between area and delay overhead of all previous designs.

Design and implementation of a high-performance 64-bit floating-point reciprocal and square root reciprocal unit

This paper designs a 64-bit floating-point reciprocal and square root reciprocal unit of a stream processor (FT64), which combines the methods of table look-up and functional iteration to implement division and square root operations. This unit which is implemented with two pipeline stages provides the initial value for the iteration of division and square root. A semi-custom and full-custom mixed design method is adopted to improve its performance, and a mixed verification method is also proposed to verify the unit. The results of verification show that the unit can achieve the performance of 1 GHz under the typical condition of 0.13 ¿m CMOS technology.

RC-Cache: Soft error mitigation techniques for low-leakage on-chip caches

This paper presents a kind of reliable low-leakage cache – RC-Cache, to solve the problem of high soft error rate in low-leakage on-chip caches. The proposed structure combines circuit technique and micro-architecture technique, and can reduce impacts of soft errors on leakage power optimization technique of caches. At circuit level, we improve the soft error immune of SRAM through specially designed soft error immune SRAM cell – SI-SRAM; at microarchitecture level, we reduce the soft error vulnerability of low-leakage caches by burst-based access prediction and early write-back operation. Experimental results show that in normal mode, soft error rate of RC-Cache is only 1/7 of the conventional cache, and in drowsy mode it is just 2/5. The techniques significantly improve the reliability of caches and, to a certain extent, mitigate soft error problem of low-leakage on-chip caches.

Exploiting idle resources for reducing SER of microprocessor functional units

Soft errors in combinational logic are becoming a serious problem for VLSI design. This paper presents an idle resources based SER reduction scheme for functional units of microprocessors. By exploiting unoccupied hardware and slack time in functional units, this technique reduces overheads of fault tolerance greatly. We combine C-element based error correction techniques with idle resources exploiting to enhance fault tolerance capability of functional units. The experiment results show that 94.36% of injected SETs can be corrected by proposed soft error correction scheme in average, while overheads of fault tolerance are significant low because idle resources are exploited adequately.

Research on the Relationship between the Effect of DPA and Differential Sample Frequency

As present, Differential Power Analysis (DPA) attack sample the power consumption information of chips using an oscilloscope which sample frequency is much larger than system global clock speed. Through the simulation of the S-box circuit in Advanced Encryption Standard (AES) and differential analysis of power consumption data, we find that, when reached an amount, the sample frequencys increasing has slight influence on the DPA. Yet when the sample frequency decreases, the cost data collected by the collection points tends to be random, which results in the correlation between the measurements of the power and the data being processed is not well revealed. Under the precondition of not impacting the effect of DPA, proper reduction in the sample frequency will not only compress the data but also increase the number of power trace. Thus the effect of the DPA is strengthened. Meanwhile, the cost of design the sampling system is reduced, which leaves more space for the improvement of the accuracy of the sampling system.

Design and implement of high fan-in logic in high-speed circuit

Two new high fan-in logics, grouped domino logic and complementary boost logic (CBL), are proposed to overcome the problem of circuit speed and noise immunity. Grouped domino logic not only speeds up the circuit, but also simplifies the design of keeper. CBL develops from source following evaluation gate (SFEG), invite complementary boost logic to speed up the circuit. In 0.13 um technology, we compare the grouped domino logic and CBL with traditional domino logic, result shows that the parameter of grouped domino logic is better than traditional domino logic, and for CBL, the unity noise gain (UNG) of CBL is about 90% of traditional domino logic whose keeper ratio is 1, but the speed of CBL is 3 times faster than domino logic.

A design of high speed AGTL+ output buffer

AGTL+ (assisted Gunning transceiver logic+) signal transmission and interface technology are analyzed in this paper. To resolve the problem on such short high-level duration time in traditional design, we have proposed an auxiliary charged circuit structure. According to what I have analyzed, we design and realize an AGTL+ interface circuit, which is completely compatible with Itanium 2 interface and has high-speed and high noise margin. The operating frequency of circuit reaches to 500MHz by SPICE simulation in the condition of 0.18mum standard CMOS process