Zhenyu Zhao

A 2.5-Gb/s 0.13-μm CMOS current mode logic transceiver with pre-emphasis and equalization

A 2.5-Gb/s current-mode logic (CML) transceiver is implemented in 0.13 - mum CMOS technology for serial inter-chip interconnection. To compensate the channel attenuation and other impairments, pre-emphasis circuit is included at the transmitter and equalizer at the receiver. 6-GHz 3 dB bandwidth is achieved through the use of active inductors instead of online spiral inductors. DC offset compensate circuits are employed in the output and input buffers to keep the common mode voltage stable. Layout simulation demonstrates the effectiveness of the transceiver. This transceiver consumes only 160 mw of power with 2.5v power supply. The die area of transmitter and receiver are 0.015 mm2, 0.01 mm2 respectively. The transceiver can be operated at 2.5-Gb/s with 100 mv receiver sensitivity.

Performance analysis of on-chip bufferless router with multi-ejection ports

In general, the bufferless NoC router has only one local output port for ejection, which may lead to multiple arriving flits competing for the only one output port. In this paper, we propose a reconfigurable bufferless router in which the number of ejection ports can be configured as 2, 3 and 4. Simulation results demonstrate that the average packet latency of the routers with multi-ejection ports is 18%, 10%, 6%, 14%, 9% and 7% on average less than that of the router with 1 ejection ports under six synthetic workloads respectively. For application workloads, the average packet latency of the router with more than two ejection ports is slightly better than the router with only one ejection port, which can be neglect. Making a compromise of hardware cost and performance, it can be concluded that it is no need to implement bufferless routers with 3 and 4 ejection ports, as the router with 2 ejection ports can achieve almost the same performance as the routers with 3 and 4 ejection ports.

A design of high speed AGTL+ output buffer

AGTL+ (assisted Gunning transceiver logic+) signal transmission and interface technology are analyzed in this paper. To resolve the problem on such short high-level duration time in traditional design, we have proposed an auxiliary charged circuit structure. According to what I have analyzed, we design and realize an AGTL+ interface circuit, which is completely compatible with Itanium 2 interface and has high-speed and high noise margin. The operating frequency of circuit reaches to 500MHz by SPICE simulation in the condition of 0.18mum standard CMOS process