Sharon Levin

Device design tradeoffs for 55v ldmos driver embedded in 0.18 micron platform

We describe the optimization of a 55 V breakdown LDMOS embedded in a 0.18 micron based power management platform. The devices self aligned structure allow the accessing low RdsOn values of 50 mohm mm2. We focus on the effects of gate poly over STI overlap which can increase the breakdown voltage by 10 V and reduce maximum substrate current 5 fold while not affecting the specific RdsOn.

Isolated silicon platforms for high current power management integrated circuit applications

We describe modular voltage and current isolation schemes in a Power Management Integrated Circuit (PMIC) silicon platform. The isolation reduces the power dissipation during switching at the high side driver. It also suppresses the cross talk between power devices switching up to 60V at several Amps, and sensitive analog / digital circuitry on the same chip. Standard, buried layer and Isolated Drain isolation schemes allow a tradeoff between the isolation level and the process complexity of the platform. The different schemes allow a current suppression ratios of 10⁁−7 in the vicinity of the Power devices or better if guard rings are combined.

Integrated Zener diode for gate protection and voltage sourcing in integrated power management platforms

We describe a Zener diode integrated in a 0.18 micron based 60V Power Management Process platform. By adding one ion implant layer, a buried diode with a sharp reverse breakdown current slope is implemented. A steep rise in reverse current, from 10−8 A to 10−3 A is obtained at the breakdown region, over less then 100mV voltage variation. The buried interface has shown no breakdown voltage shifts under prolonged stress measurements at current densities exceeding 2mA/um⁁2, shifts which were clearly observed in surface diodes. By varying the implant dose the reverse breakdown voltage — Vz, can be tuned from 4.5V to 7.5V. Consequently the diode is adequate for voltage sourcing applications and gate protection of the 5V gates utilized by the LDMOS devices in the Power Management Process.

Increase of convertor efficiency and suppression of parasitic bipolar by means of process optimization

Power Management Integrated Circuits (PMIC) chips contain large power switches - usually LDMOS transistors, along with low current control circuitry. During transistor switching, charge carriers are injected into the substrate and affect the surrounding devices. In junction isolated technologies, hole injection is effectively suppressed using highly doped n-type layers, while electron injection requires separating the highly doped layer from the drain of the device. However, this architecture forms a parasitic NPN transistor, which conducts the injected electrons to the isolation layer causing efficiency losses. We present here a method to improve the efficiency of the switch, by altering the semiconductor doping and thus tuning the gain of the parasitic bipolar. A clear tradeoff between gain and breakdown of the parasitic NPN is discussed.

Integrated high-voltage (HV) Schottky diode for power management ICs

A novel high-voltage Schottky diode is presented, which allows implementation into Silicon-based power management integrated circuits. The Schottky diode has strongly reduced leakage current at reverse bias and improved forward current under forward bias. Compared to a previous design, the forward resistance at +0.4V is reduced twofold, and at the same time, leakage current in reverse at -25V is reduced by a factor of 30 along with a smaller temperature dependency. The breakdown voltage (BV) of the device is typically >45V in reverse mode. The main element of the novel design is the application of p/n-junctions in parallel to the Schottky metal contact. Further, in forward mode under current surge conditions, the p/n-junctions protect the Schottky diode.

Integrated 60V vertical DMOS on 0.18um platform for Power over Ethernet IC

Power Management Integrated Circuits is one of the fastest growing markets in the semiconductor industry, with increasing demand for efficient electronic devices and dense integration schemes. Power over Ethernet designs are some of the most challenging, incorporating multiple channels of large High Voltage FET drivers, along with dense logic cores and high precision analog. The extreme amount of silicon area consumed by the HV drivers and the need for efficient low resistance switching has driven the need to go to area efficient vertical topologies. While vertical structures are widely implemented in discrete device manufacturing, their integration in Power Management Integrated Circuits introduces many challenges. We present a 60V platform based on a 0.18um CMOS technology, integrated with a best in class 60V vertical DMOS, providing a high performance and cost effective platform for PoE designs.

Process effective power mosfet integrated in 0.18um platform with very Low Rdson

A super Low Rdson Power transistor with high Break down voltage was developed, using double Resurf technique with low mask count.

Development of 60V PMOS for power management applications

The paper describes the development of 60V cmos transistor for 0.18-μm Power Management shallow N Buried Layer (NBL) Platform. The device has four terminals, designed to sustain 60V. While the power implants in the platform supports drain-to-source voltage up to 60V, the gate-to-source voltage is limited to 5V by the gate oxide thickness. To extend the attainable gate-to-source voltage, a local oxidation module was used to form the gate oxide. The paper addresses major process and device challenges. Feasibility experiment results are described, and a second experiment aiming to reduce the threshold voltage and increase the breakdown voltage above 80V is discussed.

Development of an N-type DEMOS on a 0.6-µm platform for 18V analog & digital aplications

Anomalous hot-carrier induced on-resistance (Ron) and drive current degradations were observed in 18 V n-type Drain Extended MOS (DEMOS) devices with various n-type Drain Drift (NDD) implant dosages. Under the same stress conditions, the device with higher NDD dosage while showing a higher substrate current (Isub) results in lower Idsat and ON-resistance (Ron) degradations. Optimal conditions for NDD implant which shift the high electric field peak causing away from the surface were introduced using technology computer aided design (TCAD) simulations. Consequently hot carrier induced degradation was suppressed as was verified by silicon measurements.