Alexey Heiman

High Density MTP Logic NVM for Power Management Applications

We report a no mask adders embedded NVM (Y-Flash) having a record cell area which is suited for power management (PM) applications. The memory cell is a self- aligned asymmetric MOS transistor with drain capacitive coupling to the floating gate (FG) through a three- dimensional extension structure. Operation of the novel memory cell, array organization, design of NVM modules and Y-Flash reliability are addressed.

Exoelectron emission from silicon nanocrystals

We have observed a high-temperature thermostimulated exoelectron emission from charged silicon nanocrystals with nitrided surface embedded into the amorphous SiO2 matrix. The developed Auger model allows understanding thermostimulated exoelectron emission origin and estimating energy activation of traps responsible for charge retention in this type of flash memory based on Si nanocrystals. The high activation energy Et of the electrons trapped in the nanocrystals confirms high potential of Si nanocrystal materials for fabrication of semiconductor memories with enhanced retention.

Isolated silicon platforms for high current power management integrated circuit applications

We describe modular voltage and current isolation schemes in a Power Management Integrated Circuit (PMIC) silicon platform. The isolation reduces the power dissipation during switching at the high side driver. It also suppresses the cross talk between power devices switching up to 60V at several Amps, and sensitive analog / digital circuitry on the same chip. Standard, buried layer and Isolated Drain isolation schemes allow a tradeoff between the isolation level and the process complexity of the platform. The different schemes allow a current suppression ratios of 10⁁−7 in the vicinity of the Power devices or better if guard rings are combined.

Increase of convertor efficiency and suppression of parasitic bipolar by means of process optimization

Power Management Integrated Circuits (PMIC) chips contain large power switches - usually LDMOS transistors, along with low current control circuitry. During transistor switching, charge carriers are injected into the substrate and affect the surrounding devices. In junction isolated technologies, hole injection is effectively suppressed using highly doped n-type layers, while electron injection requires separating the highly doped layer from the drain of the device. However, this architecture forms a parasitic NPN transistor, which conducts the injected electrons to the isolation layer causing efficiency losses. We present here a method to improve the efficiency of the switch, by altering the semiconductor doping and thus tuning the gain of the parasitic bipolar. A clear tradeoff between gain and breakdown of the parasitic NPN is discussed.

Process effective power mosfet integrated in 0.18um platform with very Low Rdson

A super Low Rdson Power transistor with high Break down voltage was developed, using double Resurf technique with low mask count.

Extending endurance of NROM memories to over 10 million program/erase cycles

We report on NROM (nitride read only) memory with enhanced endurance/retention. A novel “refresh” is introduced into the cycling algorithm to exclude parasitic electron trapping in the memory transistor. Negative gate pulses are applied when the drain voltage in the erase procedure reaches the threshold value. The memory stack is optimized to allow injection of holes from the substrate through the bottom oxide (BOX). More than 10 million program/erase (P/E) cycles with excellent retention are easily achieved.