Shye Shapira

Junction isolation for high voltage integrated circuits

We address various schemes of isolation and interconnection between high-side and low-side regions of a high-voltage gate driver integrated circuit. The main challenges are discussed. Different realizations using TS100PMHS (650V BCD technology) are presented.

High performance MEMS 0.18μm RF- CMOS inductors

This work presents the fabrication and characterization of on-chip micromachined spiral inductors in a commercially available 0.18mum CMOS process provided by TOWER Semiconductors Ltd. It explores the possibility to reduce parasitic effects and extending high frequency performance by applying a maskless micromachining post processing to create fully integrated inductors, suspended over the substrate with inter-turn dielectric removed.

Device design tradeoffs for 55v ldmos driver embedded in 0.18 micron platform

We describe the optimization of a 55 V breakdown LDMOS embedded in a 0.18 micron based power management platform. The devices self aligned structure allow the accessing low RdsOn values of 50 mohm mm2. We focus on the effects of gate poly over STI overlap which can increase the breakdown voltage by 10 V and reduce maximum substrate current 5 fold while not affecting the specific RdsOn.

CMOS DC to DC switched converter with On Chip inductors

In this study we report a monolithic buck converter power IC with on-chip ferrite core inductors. The power IC is designed and fabricated with a standard 0.18μm CMOS process. On-chip inductor with ferrite epoxy core is used as the filter inductor in the buck converter. A 5V/500mA prototype system in package (SiP) buck converter is designed to operate at frequencies up to 10MHz.

ESD protection schemes and devices embedded in a 700V integrated power management platform

This paper reviews RC and voltage triggered solutions for ESD protection of high voltage devices, embedded in TowerJazzes TS100PM 700V power management platform. The merits and limits of each solution are discussed with specific attention to the ESD design window. A scalable voltage PNP ESD protection device solution that has a trigger voltage range between 400V and 800V is presented.

VISUALIZATION OF GRAPHICAL METHODS OF SERIES ANALYSIS

Exact power series expansions provide a powerful method for studying the critical behaviour of many systems. Efficient analysis methods are essential to fully exploit the series approach. A particularly challenging problem in the analysis of these expansions is the elucidation of the critical behaviour in cases where critical temperature (or threshold) as well as dominant and correction exponent is unknown. We describe a scheme (which we call Visualization of Graphical methods for Series analysis, or VGS) developed explicitly for this situation and discuss its high precision implementation in a workstation environment. Our approach involves visualization of multiple approximants in a three-dimensional space. Several examples from Ising models, percolation and exactly solved systems are given.

High performance MEMS 0.18µm RF-CMOS transformers

This work presents a micromachined RF-CMOS transformer fabricated in a commercially available 0.18μm CMOS process. Maskless micromachining post-processing is used to remove oxide and substrate material from around the transformer, reducing parasitic effects and improving the performance of the transformer.

CMOS DC to DC switched converter with on chip inductors

We report here a study on a monolithic buck converter power IC with on-chip ferrite core inductors. The power IC is designed and fabricated with a standard 0.18μm CMOS process. On-chip inductor with ferrite core is used as the filter inductor in the buck converter. A 0.6-1.2W prototype system in package (SiP) buck converter is designed to operate at frequencies up to 10MHz.

Isolated silicon platforms for high current power management integrated circuit applications

We describe modular voltage and current isolation schemes in a Power Management Integrated Circuit (PMIC) silicon platform. The isolation reduces the power dissipation during switching at the high side driver. It also suppresses the cross talk between power devices switching up to 60V at several Amps, and sensitive analog / digital circuitry on the same chip. Standard, buried layer and Isolated Drain isolation schemes allow a tradeoff between the isolation level and the process complexity of the platform. The different schemes allow a current suppression ratios of 10⁁−7 in the vicinity of the Power devices or better if guard rings are combined.

Integrated Zener diode for gate protection and voltage sourcing in integrated power management platforms

We describe a Zener diode integrated in a 0.18 micron based 60V Power Management Process platform. By adding one ion implant layer, a buried diode with a sharp reverse breakdown current slope is implemented. A steep rise in reverse current, from 10−8 A to 10−3 A is obtained at the breakdown region, over less then 100mV voltage variation. The buried interface has shown no breakdown voltage shifts under prolonged stress measurements at current densities exceeding 2mA/um⁁2, shifts which were clearly observed in surface diodes. By varying the implant dose the reverse breakdown voltage — Vz, can be tuned from 4.5V to 7.5V. Consequently the diode is adequate for voltage sourcing applications and gate protection of the 5V gates utilized by the LDMOS devices in the Power Management Process.