Shashank Gupta

A Comparative Study of Different Physics-Based NBTI Models

Different physics-based negative bias temperature instability (NBTI) models as proposed in the literature are reviewed, and the predictive capability of these models is benchmarked against experimental data. Models that focus exclusively on hole trapping in gate-insulator-process-related preexisting traps are found to be inconsistent with direct experimental evidence of interface trap generation. Models that focus exclusively on interface trap generation are incapable of predicting ultrafast measurement data. Models that assume strong correlation between interface trap generation and hole trapping in switching hole traps cannot simultaneously predict long-time dc stress, recovery, and ac stress and cannot estimate gate insulator process impact. Uncorrelated contributions from generation and recovery of interface traps, together with hole trapping and detrapping in preexisting and newly generated bulk insulator traps, are invoked to comprehensively predict dc stress and recovery, ac duty cycle and frequency, and gate insulator process impact of NBTI. The reaction-diffusion model can accurately predict generation and recovery of interface traps for different devices and experimental conditions. Hole trapping/detrapping is modeled using a two-level energy well model.

Fermi level depinning and contact resistivity reduction using a reduced titania interlayer in n-silicon metal-insulator-semiconductor ohmic contacts

Experimental evidence of reduction of ultrathin TiO2 by Ti is presented and its effect on Fermi level depinning and contact resistivity reduction to Si is experimentally studied. A low effective barrier height of 0.15 V was measured with a Ti/10 A TiO2−x/n-Si MIS device, indicating 55% reduction compared to a metal/n-Si control contact. Ultra-low contact resistivity of 9.1 × 10−9 Ω-cm2 was obtained using Ti/10 A TiO2−x/n+ Si, which is a dramatic 13X reduction from conventional unannealed contacts on heavily doped Si. Transport through the MIS device incorporating the effect of barrier height reduction and insulator conductivity as a function of insulator thickness is comprehensively analyzed and correlated with change in contact resistivity. Low effective barrier height, high substrate doping, and high conductivity interfacial layer are identified as key requirements to obtain low contact resistivity using MIS contacts.

Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts

Metal-induced-gap-states model for Fermi-level pinning in metal-semiconductor contacts has been extended to metal-interfacial layer (IL)-semiconductor (MIS) contacts using a physics-based approach. Contact resistivity simulations evaluating various ILs on n-Ge indicate the possibility of forming low resistance contacts using TiO2, ZnO, and Sn-doped In2O3 (ITO) layers. Doping of the IL is proposed as an additional knob for lowering MIS contact resistance. This is demonstrated through simulations and experimentally verified with circular-transfer length method and diode measurements on Ti/n+-ZnO/n-Ge and Ti/ITO/n-Ge MIS contacts.

Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a ~2× improvement in static random-access memory and digital input/ output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.

56 Gb/s Germanium Waveguide Electro-Absorption Modulator

We report a Germanium waveguide electro-absorption modulator with electro-optic bandwidth substantially beyond 50 GHz. The device is implemented in a fully integrated Si photonics platform on 200 mm silicon-on-insulator wafers with 220 nm top Si thickness. Wide open eye diagrams are demonstrated at 1610 nm operation wavelength for nonreturn-to-zero on-off keying (NRZ-OOK) modulation at data rates as high as 56 Gb/s. Dynamic extinction ratios up to 3.3 dB are obtained by applying drive voltages of 2 V peak-to-peak, along with an optical insertion loss below 5.5 dB. The device has a low junction capacitance of just 12.8 fF, resulting in 12.8 fJ/bit of dynamic and ~1.2 mW of static power consumption in typical operating conditions. Wafer-scale performance data are presented and confirm the manufacturability of the device. The demonstrated modulator shows great potential for realizing high-density and low-power silicon photonic transceivers targeting short-reach optical interconnects at serial data rates of 56 Gb/s and beyond.

Direct Bandgap Light Emission from Strained Germanium Nanowires Coupled with High-Q Nanophotonic Cavities

A silicon-compatible light source is the final missing piece for completing high-speed, low-power on-chip optical interconnects. In this paper, we present a germanium nanowire light emitter that encompasses all the aspects of potential low-threshold lasers: highly strained germanium gain medium, strain-induced pseudoheterostructure, and high-Q nanophotonic cavity. Our nanowire structure presents greatly enhanced photoluminescence into cavity modes with measured quality factors of up to 2000. By varying the dimensions of the germanium nanowire, we tune the emission wavelength over more than 400 nm with a single lithography step. We find reduced optical loss in optical cavities formed with germanium under high (>2.3%) tensile strain. Our compact, high-strain cavities open up new possibilities for low-threshold germanium-based lasers for on-chip optical interconnects.

Using the PiP Model for Fast Calculation of Vibration from a Railway Tunnel in a Multi-layered Half-Space

This paper presents a new method for calculating vibration from underground railways buried in a multi-layered half-space. The method assumes that the tunnel’s near-field displacements are controlled by the dynamics of the tunnel and the layer that contains the tunnel, and not by layers further away. Therefore the displacements at the tunnel-soil interface can be calculated using a model of a tunnel embedded in a full space. The Pipe-in-Pipe (PiP) model is used for this purpose, where the tunnel wall and its surrounding ground are modelled as two concentric pipes using elastic continuum theory. The PiP model is computationally efficient on account of uniformity along and around the tunnel. The far-field displacement is calculated by using another computationally efficient model that calculates Green’s functions for a multi-layered half-space using the direct stiffness method. The model is based on the exact solution of Navier’s equations for a horizontally layered half-space in the frequency-wavenumber domain.

Study of Carrier Statistics in Uniaxially Strained Ge for a Low-Threshold Ge Laser

In this paper, we present a comprehensive study of carrier statistics in germanium with high uniaxial strain along the [100] direction. Several types of PL experiments were conducted to investigate polarization-, temperature- and excitation-dependent carrier statistics in germanium under various amounts of uniaxial strain. With the ability to clearly resolve multiple photoluminescence peaks originating from strain-induced valence band splitting, we experimentally observed strongly polarized light emission from direct band gap transitions. Our experiments also confirm that uniaxial strain increases the hole population in the highest valence band as well as the electron population in the direct conduction band. Based upon our experimental results, we present theoretical modeling showing that the lasing threshold of a germanium laser can be reduced by >100× with 2.5% strain.

ZnO: an attractive option for n-type metal-interfacial layer-semiconductor (Si, Ge, SiC) contacts

We propose ZnO as an attractive interfacial layer (IL) option for n-type metal-IL-semiconductor (MIS) contacts because of (i) good conduction band alignment between ZnO and Si/Ge/SiC, (ii) high n-type doping possible in ZnO, and, (iii) low Fermi-level pinning factor for metal/ZnO contacts. Device simulations suggest better scalability for MIS contacts versus silicides/germanides for future FinFET technologies. Contact diode measurements on Ti/n⁺-ZnO/n-Ge and Ti/n⁺-ZnO/n-Si devices show nearly 1000X increase in current densities due to the presence of an n⁺-ZnO IL. In comparison to alternate IL options such as Al₂O₃ and TiO₂, n⁺-ZnO gives significantly higher current densities on n-Ge as demonstrated through device simulations and experimental data. Specific contact resistivity of (0.8-1.5) × 10^-6 Ω cm² is demonstrated through four-probe measurements on circular TLM devices fabricated on n⁺-Ge (1 × 10¹⁹ cm^-3) epi layers using n⁺-ZnO IL.

Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks

S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled FinFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in FinFET devices for the 22nm node and remain effective with conservative scaling of contact / gate CD only.