Shaunee Cheng

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

We present results from investigating critical challenges of pitch doubling through Double Patterning to meet manufacturing requirements for 32nm 1/2 pitch on 1.2NA lithography system. Simulations of lithography alternatives identified manufacturable Dose-Focus latitudes for a dual-line positive process option which led to an experimental setup based on a single hardmask process. Key challenges of the selected process relate to the presence or absence of the hardmask layer during 1st or 2nd patterning step. This has an effect on wafer topography, process setup, etch bias and wafer litho-to-etch CDU offsets, which will create two final CDU populations. Therefore, there are two metrology challenges, separation between the two CD populations and overlay-at-resolution using CDSEM. They were addressed by designing appropriate CD and overlay targets and by implementing an adequate dense sampling allowing modeling of wafer and field CD distributions. We introduced a new CDU model to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance. For a single line and 1.35NA system, the model predicted 3.1nm variance with mask CDU and etch bias being the major contributors. We achieved an experimental resolution of 32-nm 1/2 pitch on 1.2NA system, which equals 0.20k1. Experimental results at 32-nm resolution were confirmed in a pre-manufacturing environment on a full lot of 24 wafers, with raw CDU of 6nm (3s). After modeling and correcting for interfield (wafer) and intrafield spatial distributions, CDU was improved to 2.5nm (3s). Best overlay results equaled scanner SMO capability of ~7nm (mean+3s).

Split and design guidelines for double patterning

Double Patterning is investigated at IMEC as a timely solution to meet the 32nm node requirements. It further extends the use of water immersion lithography at its maximum numerical aperture NA=1.35. The aim of DP is to make dense features possible by splitting a design into two more sparse designs and by recombining into the target pattern through a double patterning flow (stitching). Independently of the implementation by the EDA vendors and designers, we discuss some guidelines for split and for DP-compliant design to ensure a robust stitching through process variations. We focus more specifically on the first metal interconnect patterning layer (metal1) for random logic applications. We use both simulations and experiments to study the patterning of 2D split test patterns varied in a systematic way.

Double patterning lithography for 32 nm: critical dimensions uniformity and overlay control considerations

Double patterning lithography (DPL)-either with two litho and two etches or through the use of a sacrificial spacer-are comparable in complexity and process control requirements. Since critical dimensions uniformity (CDU) and overlay requirements are considerably tighter than in single exposure, they present tougher challenges to process control, metrology, and integration, but seem feasible for 32-nm node. We study CDU and overlay requirements and performance at 32-nm-hp resolution for dual litho-etch and sacrificial spacer schemes. We bring in three particular aspects of CD control: the existence of multiple populations of lines and spaces, overlay entanglement into CDU performance, and the mechanism of doubled-pitch pattern generation from uncorrelated left and right edges, Accordingly, active compensation schemes are proposed to bring together these multiple CDU populations in order to achieve the typical 10% CD tolerance of the final pattern. Experimental results confirmed our assumptions of CDU-overlay entanglement and existence of multiple CD populations of lines and spaces. We present CDU results from before and after applying CD compensation schemes to improve CDU and overlay performance through active feed forward corrections. Results confirm the gain in improving statistical and spatial CD distribution to meet control levels required at 32-nm design rules: 2-nm CDU control per population, 3-nm CDU control for two adjacent lines, or spacer CD populations with 3-nm single machine overlay, all of them being demonstrated on multiple wafers and immersion scanners.

Double patterning for 32nm and below: an update

Double patterning lithography - either with two litho and etch steps or through the use of a sacrificial spacer layer, have equal complexity and particularly tight requirements on CDU and Overlay. Both techniques pose difficult challenges to process control, metrology and integration, but seem feasible for the 32nm node. In this paper, we report results in exploring CDU and overlay performance at 32nm 1/2 pitch resolution of two double patterning technology options, Dual Photo Etch, LELE and sidewall spacer with sacrificial layer. We discuss specific aspects of CD control present in any double patterning lithography, the existence of multiple populations of lines and spaces, with overlay becoming part of CDU budget. The existence of multiple and generally uncorrelated CD populations, demands utilization of full field and full wafer corrections to bring together the CDU of these multiple populations in order to meet comparable 10% CDU as in single exposure. We present experimental results of interfield and intrafield CD and overlay statistical and spatial distributions confirming capability to improve these distributions to meet dimensional and overlay control levels required by 32nm node. After compensation, we achieved a CDU control for each population, of 2nm or better and 3nm overlay on multiple wafers and multiple state of art, hyper NA immersion scanners. Results confirmed our assumptions for existence of multiple CDU populations entangled overlay into CDU.

Sources of Overlay Error in Double Patterning Integration Schemes

With the planned introduction of double patterning techniques, the focus of attention has been on tool overlay performance and whether or not this meets the required overlay for double patterning. However, as we require tighter and tighter overlay performance, the impact of the selected integration strategy plays a key part in determining the achievable overlay performance. Very little attention has been given at this time to the impact of for example deposition steps, oxidation steps, CMP steps and the impact that they have on wafer deformation and therefore degraded overlay performance, which directly reduces the available overlay budget. Also, selecting the optimum alignment strategy to follow, either direct or indirect alignment, plays an important part in achieving optimum overlay performance. In this paper we investigate the process impact of various double patterning integration strategies and attempt to show the importance of selecting the right strategy with respect to achieving a manufacturable double patterning process. Furthermore, we report a methodology to minimize process overlay by modelling the non-linear grids for process induced wafer deformation and demonstrate best achievable overlay by feeding this information back to the relevant process steps.

Natural EUV mask blank defects: evidence, timely detection, analysis and outlook

A combination of blank inspection (BI), patterned mask inspection (PMI) and wafer inspection (WI) is used to find as many as possible printing defects on two different EUV reticles. These multiple inspections result in a total population of known printing defects on each reticle. The printability of these defects is first confirmed by wafer review on wafers exposed on the full field ASML Alpha Demo Tool (ADT) at IMEC. Subsequently reticle review is performed on the corresponding locations with both SEM (Secondary Electron Microscope) and AFM (Atomic Force Microscope). This review methodology allows to separate absorber related mask defects and multi layer (ML) related mask defects. In this investigation the focus is on ML defects, because this type of reticle defects is EUV specific, and not as evolutionary as absorber defects which can be mitigated in more conventional ways. This work gives evidence of critical printing ML defects of natural origin, both pits as shallow as 3nm and bumps just 3nm high at the surface. Wafer inspection was the first inspection technique to detect these ML-defects with marginal surface height distortion, because both state-of-the-art PMI and especially standard BI on the Lasertec M1350 had failed to detect these defects. Compared to standard BI, the more advanced Lasertec M7360 is found to have much better sensitivity for printing MLdefects and our work so far shows no evidence of printing ML defects missed by this tool. Unfortunately it was also observed that this required sensitivity was only achieved at the cost of an unacceptable nuisance rate, i.e., with a too high number of detections of non-printing defects. Optical blank inspection is facing major challenges : It needs not only to find ML defects with height distortions of 3nm and less (and in theory maybe even 0nm), but also it must be able to disposition between such likely-printing and non-printing defects.

Progress in EUV lithography towards manufacturing from an exposure tool perspective

EUV lithography is a candidate for device manufacturing for the 16nm node and beyond. To prepare for insertion into manufacturing, the challenges of this new technology need to be addressed. Therefore, the ASML NXE:3100 preproduction tool was installed at imec replacing the ASML EUV Alpha Demo Tool (ADT). Since the technology has moved to a pre-production phase, EUV technology has to mature and it needs to meet the strong requirements of sub 16nm devices. We discuss the CD uniformity and overlay performance of the NXE:3100. We focus on EUV specific contributions to CD and overlay control, that were identified in earlier work on the ADT. The contributions to overlay originate from the use of vacuum technology and reflective optics inside the scanner, which are needed for EUV light transmission and throughput. Because the optical column is in vacuum, both wafer and reticle are held by electrostatic chucks instead of vacuum chucks and this can affect overlay. Because the reticle is reflective, any reticle (clamp) unflatness directly translates into a distortion error on wafer (non-telecentricity). For overlay, the wafer clamping performance is not only determined by the exposure chuck, but also by the wafer type that is used. We will show wafer clamping repeatability with different wafer types and discuss the thermal stability of the wafer during exposure.

Diffraction based overlay metrology: accuracy and performance on front end stack

The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay metrology total measurement uncertainty requirements of 0.57 nm for the most challenging use cases of the 32nm technology generation. Theoretical considerations show that overlay technology based on differential signal scatterometry (SCOLTM) has inherent advantages, which will allow it to achieve the 32nm technology generation requirements and go beyond it. In this work we present results of an experimental and theoretical study of SCOL. We present experimental results, comparing this technology with the standard imaging overlay metrology. In particular, we present performance results, such as precision and tool induced shift, for different target designs. The response to a large range of induced misalignment is also shown. SCOL performance on these targets for a real stack is reported. We also show results of simulations of the expected accuracy and performance associated with a variety of scatterometry overlay target designs. The simulations were carried out on several stacks including FEOL and BEOL materials. The inherent limitations and possible improvements of the SCOL technology are discussed. We show that with the appropriate target design and algorithms, scatterometry overlay achieves the accuracy required for future technology generations.

Further investigation of EUV process sensitivities for wafer track processing

As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, its shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

Overlay metrology for double patterning processes

The double patterning (DPT) process is foreseen by the industry to be the main solution for the 32 nm technology node and even beyond. Meanwhile process compatibility has to be maintained and the performance of overlay metrology has to improve. To achieve this for Image Based Overlay (IBO), usually the optics of overlay tools are improved. It was also demonstrated that these requirements are achievable with a Diffraction Based Overlay (DBO) technique named SCOLTM [1]. In addition, we believe that overlay measurements with respect to a reference grid are required to achieve the required overlay control [2]. This induces at least a three-fold increase in the number of measurements (2 for double patterned layers to the reference grid and 1 between the double patterned layers). The requirements of process compatibility, enhanced performance and large number of measurements make the choice of overlay metrology for DPT very challenging. In this work we use different flavors of the standard overlay metrology technique (IBO) as well as the new technique (SCOL) to address these three requirements. The compatibility of the corresponding overlay targets with double patterning processes (Litho-Etch-Litho-Etch (LELE); Litho-Freeze-Litho-Etch (LFLE), Spacer defined) is tested. The process impact on different target types is discussed (CD bias LELE, Contrast for LFLE). We compare the standard imaging overlay metrology with non-standard imaging techniques dedicated to double patterning processes (multilayer imaging targets allowing one overlay target instead of three, very small imaging targets). In addition to standard designs already discussed [1], we investigate SCOL target designs specific to double patterning processes. The feedback to the scanner is determined using the different techniques. The final overlay results obtained are compared accordingly. We conclude with the pros and cons of each technique and suggest the optimal metrology strategy for overlay control in double patterning processes.