Anne-Laure Charley

Focus and dose deconvolution technique for improved CD control of immersion clusters

As critical dimension (CD) control requirements increase and process windows decrease, it is now of even higher importance to be able to determine and separate the sources of CD error in an immersion cluster, in order to correct for them. It has already been reported that the CD error contributors can be attributed to two primary lithographic parameters: effective dose and focus. In this paper, we demonstrate a method to extract effective dose and focus, based on diffraction based optical metrology (scatterometry). A physical model is used to describe the CD variations of a target with controlled focus and dose offsets. This calibrated model enables the extraction of effective dose and focus fingerprints across wafer and across scanner exposure field. We will show how to optimize the target design and the process conditions, in order to achieve an accurate and precise de-convolution over a larger range of focus and dose than the expected variation of the cluster. This technique is implemented on an ASML XT:1900Gi scanner interfaced with a Sokudo RF3S track. The systematic focus and dose fingerprints obtained by this de-convolution technique enable identification of the specific contributions of the track, scanner and reticle. Finally, specific corrections are applied to compensate for these systematic CD variations and a significant improvement in CD uniformity is demonstrated.

Enabling CD SEM metrology for 5nm technology node and beyond

The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

High-speed, full 3D feature metrology for litho monitoring, matching, and model calibration with scatterometry

We studied the potential of optical scatterometry to measure the full 3D profile of features representative to real circuit design topology. The features were selected and printed under conditions to improve the measurability of the features by scatterometry without any loss of information content for litho monitoring and control applications. The impact of the scatterometry recipe and settings was evaluated and optimal settings were determined. We have applied this strategy on a variety of structures and gathered results using the YieldStar angular reflection based scatterometer. The reported results show that we obtained effective decoupling of the measurement of the 3 dimensions of the features. The results match with predictions by calibrated lithographic simulations. As a verification we have successfully performed a scanner matching experiment using computational Pattern Matcher (cPM) in combination with YieldStar as a metrology tool to characterize the difference between the scanners and verify the matching. The results thus obtained were better than using CD-SEM for matching and verification.

Line-end gap measurement with YieldStar scatterometer: towards an OPC model calibration

Line-end gap measurement for OPC calibration is a challenge for metrology. Even for CD-SEM, the rounded shape of the line end makes it very difficult to measure precisely. We have presented preliminary results of the application of scatterometry to these challenging structures using an angle resolved polarized scatterometer: ASML YieldStar [1]. In this paper, the exercise was extended to several different structures combining multiple line-end gap situations. Systematic comparison with CD-SEM is performed and discussed. Lithographic behavior of the main parameters is analyzed. Strengths and limits of the technique will be shown. Once validated, the metrology is used to build an OPC model and correct our test vehicle.

3D features measurement using YieldStar: an angle resolved polarized scatterometer

Metrology on 3D features like line end gap in a SRAM structure is more challenging than on lines and spaces (L/S) structures. Scatterometry has been widely used on L/S structures and has enabled characterization of lithographic features providing with critical dimensions (CD) as well as feature height and side wall angle. In this paper, we will present the application of scatterometry to these challenging structures using an angle resolved polarized scatterometer: ASML YieldStar S-100. 3D features (line ends, brick walls,...) measurements will be presented. Measurement capability will be discussed in terms of sensitivity of the parameters of interest and correlation between them leading to a proper model choice.

The need for LWR metrology standardization: the imec roughness protocol

As semiconductor technology keeps moving forward, undeterred by the many challenges ahead, one specific deliverable is capturing the attention of many experts in the field: Line Width Roughness (LWR) specifications are expected to be less than 2nm in the near term, and to drop below 1nm in just a few years. This is a daunting challenge and engineers throughout the industry are trying to meet these targets using every means at their disposal. However, although current efforts are surely admirable, we believe they are not enough. The fact is that a specification has a meaning only if there is an agreed methodology to verify if the criterion is met or not. Such a standardization is critical in any field of science and technology and the question that we need to ask ourselves today is whether we have a standardized LWR metrology or not. In other words, if a single reference sample were provided, would everyone measuring it get reasonably comparable results? We came to realize that this is not the case and that the observed spread in the results throughout the industry is quite large. In our opinion, this makes the comparison of LWR data among institutions, or to a specification, very difficult. In this paper, we report the spread of measured LWR data across the semiconductor industry. We investigate the impact of image acquisition, measurement algorithm, and frequency analysis parameters on LWR metrology. We review critically some of the International Technology Roadmap for Semiconductors (ITRS) metrology guidelines (such as measurement box length larger than 2μm and the need to correct for SEM noise). We compare the SEM roughness results to AFM measurements. Finally, we propose a standardized LWR measurement protocol - the imec Roughness Protocol (iRP) - intended to ensure that every time LWR measurements are compared (from various sources or to specifications), the comparison is sensible and sound. We deeply believe that the industry is at a point where it is imperative to guarantee that when talking about a critical parameter such like LWR, everyone speaks the same language, which is not currently the case.

Innovative scatterometry approach for self-aligned quadruple patterning (SAQP) process control

In this work, capabilities of scatterometry at various steps of the self-aligned quadruple patterning (SAQP) process flow for 7nm (N7) technology node are demonstrated including the pitch walk measurement on the final fin etch step. The scatterometry solutions for each step are verified using reference metrology and the capability to follow the planned process design-of-experiment (DOE) and the sensitivity to catch the small process variations are demonstrated. Pitch walk, which is pitch variation in the four line/space (L/S) populations, is one of the main process challenges for SAQP. Scatterometry, which is a versatile optical technique for critical dimensions (CD) and shape metrology, can find the direct measurement of pitch walk challenging because it is a very weak parameter. In this work, the pitch walk measurement is managed via scatterometry using an advanced technique of parallel interpretation of scatterometry pads with varying pitches. The three populations of trenches could be clearly distinguished with the scatterometry and the consistency with the reference data and with the process DOE are presented. In addition, the root cause of the within-wafer non-uniformity of fin CD is determined. The measurements were done on-site at IMEC as a part of the process development and control of the IMEC SAQP processes [1]. All in all, in this work it is demonstrated that scatterometry is capable of monitoring each process step of FEOL SAQP and it can measure three different space populations separately and extract pitch walk information at the final fin etch step.

High speed optical metrology solution for after etch process monitoring and control

Monitoring and control of the various processes in the semiconductor require precise metrology of relevant features. Optical Critical Dimension metrology (OCD) is a non-destructive solution, offering the capability to measure profiles of 2D and 3D features. OCD has an intrinsic averaging over a larger area, resulting in good precision and suppression of local variation. We have studied the feasibility of process monitoring and control in AEI (after etch inspection) applications, using the same angular resolved scatterometer as used for CD, overlay and focus metrology in ADI (after develop inspection) applications1. The sensor covers the full azimuthal-angle range and a large angle-of-incidence range in a single acquisition. The wavelength can be selected between 425nm and 700nm, to optimize for sensitivity for the parameters of interest and robustness against other process variation. In this paper we demonstrate the validity of the OCD data through the measurement and comparison with the reference metrology of multiple wafers at different steps of the imec N14 fabrication process in order to show that this high precision OCD tool can be used for process monitoring and control.

Advanced CD-SEM solution for edge placement error characterization of BEOL pitch 32nm metal layers

Metrology plays an important role in edge placement error (EPE) budgeting. Control for multi-patterning applications as new critical distances needs to be measured (edge to edge) and requirements become tighter and tighter in terms of accuracy and precision. In this paper we focus on imec iN7 BEOL platform and particularly on M2 patterning scheme using SAQP + block EUV for a 7.5 track logic design. Being able to characterize block to SAQP edge misplacement is important in a budgeting exercise (1) but is also extremely difficult due to challenging edge detection with CD-SEM (similar materials, thin layers, short distances, 3D features). In this study we develop an advanced solution to measure block to SAQP placement, we characterize it in terms of sensitivity, precision and accuracy through the comparison to reference metrology. In a second phase, the methodology is applied to budget local effects and the results are compared to the characterization of the SAQP and block independently.

Scatterometry for gate all around (GAA) technology enablement (Conference Presentation)

Future of logic silicon extension lies at the heart of gate all around developments (1). Due to the increasing limitations in further FinFET flow extension, teams around the globe are researching with vertical and horizontal nanowires flavors. Horizontal NW are of great interest due to their integration similarity to the existing FinFET integration flow (2). This in turn allows to extend the usage of existing process and metrology platforms, and reduce the cost of shifting to a new technology. Even though the integration changes seem limited, it springs many new obstacle for fab metrology. New parameters of interest take place, and the metrology capability needs to reach higher performance, and develop new solution methods (3,4). The current paper will focus on one of the new rising metrology challenges, which exist at the nanowire release process step. The nanowire release step, a SiGe dummy layer is being removed by dry etching, to leave behind the active Silicon nanowires, for nfet device. A detailed metrology of these nanowire profile and thickness is required to verify the device can perform to the expected specifications. To examine the scatterometry performance at this application, a specific design of experiment was set, at multiple process step. at fin formation we begin with split condition, on the silicon-silicon germanium (Si-SiGe) multi layer deposition, where SiGe , are being varied between wafers, by increasing the SiGe layer thickness, thus different amount of SiGe material will be released (figure 1a). Scatterometry and X-ray reflectivity (XRR) are verifying this split condition (figure 1b). We continue with additional split condition for the fin reveal, allowing the lower SiGe layer to be more or less revealed to the SiGe release etching step (figure 2a). To confirm the fin height for the different splits condition we use atomic force microscope (AFM), and scatterometry (figure 2b). the last process DoE we report is the etching method in which the SiGe is released. The two etch methods, we address in this paper, provides different nanowire profile (figure 3), a circular or rectangular shapes, respectively. The last part of this paper will highlight how scatterometry nanowire profile accuracy, at the SiGe release step, is improved by incorporating the complete GAA steps scatterometry solutions, and the combination of Transmission electron microscopy (TEM) rich sampling.