Monique Ercken

Line edge roughness: characterization, modeling and impact on device behavior

Simple analytical expressions are presented, which calculate the impact of line edge roughness on MOSFET parameter fluctuations. It is experimentally demonstrated that LER has no impact on 80 nm gate length transistors. Simulations show LER to become significant for 32 nm channel length devices.

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

Multiple gate field effect transistors (MuGFET) with a fin pitch down to 50nm obtained with 193nm optical lithography and proposed fin quadrupling patterning method are demonstrated. The fins patterned with this technique feature improved CD control and line width roughness. High fin density in combination with Si-SEG that allows merging individual fins outside the spacer region lead to reduction in parasitic source/drain-resistance and 3-fold increase in drive current per surface unit

Novel process to pattern selectively dual dielectric capping layers using soft-mask only

We are reporting for the first time on the use of simple resist-based selective high-k dielectric capping removal processes of La₂O₃, Dy₂O₃ and Al₂O₃ on both HfSiO(N) and SiO₂ to fabricate functional HK/MG CMOS ring oscillators with 40% fewer process steps compared to our previous report [1]. Both selective high-k removal (using wet chemistries) and resist strip processes (using NMP and APM) have been characterized physically and electrically indicating no major impact on Vt, EOT, Jg, mobility and gate dielectric integrity (PBTI, TDDB and charge pumping).

Spectral analysis of line width roughness and its application to immersion lithography

Various approaches can be used to quantify line width rough- ness LWR. One of the most commonly used estimators of LWR is standard deviation . However, a substantial amount of information is ignored if only is measured. We use an automated approach to inves- tigate LWR, where standard deviation, correlation length, and power spectrum are measured online on critical dimension scanning electron microscopes. This methodology is used to monitor LWR, investigate the effect of LWR on critical dimension precision, and to benchmark new resists for immersion lithography. Our results indicate that online LWR metrology is a critical tool in a variety of applications, including but not restricted to process control.

High yield sub-0.1µm 2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

Spintronic majority gates

In this paper we present an overview of two types of majority gate devices based on spintronic phenomena. We compare the spin torque majority gate and the spin wave majority gate and describe work on these devices. We discuss operating conditions for the two device concepts, circuit implication and how these reflect on materials choices for device implementation.

Full-field EUV and immersion lithography integration in 0.186μm 2 FinFET 6T-SRAM cell

We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM VDD scalability down to 0.6V (SNM>0.1VDD) and healthy electrical characteristics (VT, sigma(DeltaVT), I-V) for the cell transistors are obtained.

Dry Etch Fin Patterning of a Sub-22nm Node SRAM Cell: EUV Lithography New Dry Etch Challenges

This work describes the dry etching process for patterning crystalline Silicon (c-Si) on a 6T-SRAM cell using Extreme UV (EUV) lithography. The target fins consist of straight structures (30nm height and 15nm of critical dimension) patterned on a sub-22nm node with 80nm fin pitch. Scaling down the fin pitch had a direct influence on the fin critical dimension and profile. We found out that the fin etching process developed for a 22nm node process with 90nm fin pitch was no longer functional for patterning fins on a sub-22nm node with 80nm fin pitch. In order to pattern straight fins with 15nm of critical dimension, we had to improve the selectivity towards EUV photo resist, redesign the patterning stack thickness and eliminate the typical softlanding step used in previous nodes.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I_OFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (W_NW≤25nm, H_NW~22nm), with increased doping enabling ION improvement without I_OFF penalty for W_NW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. V_T mismatch performance shows higher A_VT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (d_NW≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low I_OFF, I_G, and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.

Challenges and opportunities of vertical FET devices using 3D circuit design layouts

We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values as compared to cells built with lateral GAA-NWFETs. Furthermore, vertical stacking of these devices also opens the path for SRAM 3D scaling, with a design presented here that can enable, with two levels of transistors in the vertical direction, to reduce by 39% the SRAM area per bit. The two vertically stacked VNWFETs are of the same doping type (n/n or p/p), and a lower complexity of implementation may be possible by taking advantage of the junctionless (JL) concept and its process simplicity, a topic also explored in this work.