Shawn Chang

Robust design of HV pLDMOS-ESCR structures in a 60-V BCD process

A pMOS transistor can be used as an electrostatic discharge (ESD) protection device; however, due to its higher turn-on resistance, it has a poor ESD robustness than that of nMOS transistors. Nevertheless, for a high-voltage (HV) p-channel laterally-diffused MOS (pLDMOS), which has a low impact-ionization rate, almost a non-snapback phenomenon (high Vh value) and then with a high latch-up (LU) immunity. What is happening if a pLDMOS embedded with an HV silicon-controlled rectifier (ESCR)? In this paper, a novel HV pLDMOS-ESCR is proposed by implanted an extra N+ diffusion region in the drain-side among a pLDMOS. Meanwhile, the location of the N+ diffusion region is changed in order to investigate the impact on ESD capability. And, in this work, three different unit finger widths will be evaluated. Eventually, the It2 value of “pnp”-type among HV pMOS-ESCR will be four times higher than that of “npn”-type at least, in the same time, the Vh value of “pnp”-type HVpMOS-ESCR higher than that of “npn”-type, too. Therefore, the “pnp”-type HV pLDMOS-ESCR structure is an excellent structure in the HV technology due to its high ESD and latch-up immunities.

ESD reliability comparison of different layout topologies in the 0.25-μm 60-V nLDMOS power devices

The impact of layout-type dependences on anti-ESD robustness in a 0.25 μm 60 V process will be investigated in this paper, which included the traditional striped-type nLDMOS, waffle-type nLDMOS, and nLDMOS embedded with a pnp-manner SCR devices. Then, these nLDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh) and secondary breakdown current (It2). Eventually, it can be found that how to sketch the layout pattern of an nLDMOS is a very important issue in the anti-ESD consideration. The waffle-type nLDMOS DUT is poor contribution to It2 robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the It2 robustness of a waffle-type nLDMOS device is decreased about 17% as compared with a traditional striped-type (reference) nLDMOS device. The ESD abilities of traditional striped-type and waffle-type nLDMOS devices with an embedded SCR (pnp-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR (pnp-manner arrangement) is a good structure for the anti-ESD reliability in high-voltage applications.

Robust reliability and electrical performances by the bulk-contact modulation in 60-V p-channel LDMOS power components

ABSTRACT To increase reliability and electrical performance, shallow-trench isolation (STI) (or called field-oxide (FOX)) structures were inserted in the bulk-contact region of 60-V high-voltage p-channel lateral-diffused MOSFET (pLDMOS) devices in this study. As the FOX ratio increased with the addition of FOX segments, the value of the secondary breakdown current (It2) was enhanced. Therefore, the anti-electrostatic discharge ability of a pLDMOS device can be efficiently improved using this novel method. In addition, when the weighting ratio of FOX structures increased, variation values in the trigger voltage (Vt1) and holding voltage (Vh) of the corresponding samples remained within the range of approximately 1–4 V. The Ron value decreased because of more uniform conduction. The experimental data for the FOX structures added to the bulk revealed that the It2 value was improved by approximately 13.98%, Vh values were greater than 60 V (which is favorable for latch-up immunity), and the Ron value was decreased by approximately 12.62% compared with a reference device under test (without FOX segments in the bulk-contact region).

Anti-ESD Improvement by the Bulk-FOX Structure in HV nLDMOS Devices

This work is focused on a 0.25 μm 60 V high-voltage nLDMOS devices which will be integrated with a FOX structure in the bulk region, and evaluate the impacts on its anti-ESD protection ability. It is found that as an FOX sturcture adding, and as the FOX area ratio is increased, It2 value will be enhanced too. When the FOX area ratio is about 83.5 %, It2 value has a maximum value ~6A. However, as the FOX area ratio is increased, the Ron value will be declined. From the experimental data, it is revealed that Vt1 (Vh) value decreased more than 16.9 % (35.6 %), anti-ESD ability increased more than 170.2 %, and Ron decreased more than 81.2 % as compared with the Ref. DUT.

N+ Extended-Distribution Influences on Anti-ESD Ability in the 60-V pLDMOS-SCR (NPN-Arranged-Type)

In order to effectively improve the reliability capability, a p-channel lateral-diffused MOSFETs with an embedded SCR which is formed by implanting N+ doses in the both sides of the drain end, and this structure called as the npn-arranged-type of pLDMOS-SCR in this chapter (diffusion region of drain-side is N+-P+-N+). Then, changing the layout manner of N+ implants in both sides of a drain-side P+ region is investigated in this chapter by a 0.25-μm 60-V BCD process. In this planning idea, the layout types of N+ region are continuously extended into the drain-side. From the experimental results, due to all of their secondary breakdown current (It2) values are so good that reached above 7 A, it can be found that the layout manner of continuous extended types in the drain-side have a little impact on the ESD capability. However, the major repercussion is the Vh value will be decreased about 10.8–49.5 %.

ESD reliability building in 0.25 μm 60-V p-channel LDMOS DUTs with different embedded SCRs

In order to effectively improve the ESD capability of a p-channel lateral-diffused MOS device, we aimed at the anti-ESD protection capability of the different layout types in the drain-side for the 0.25-μm 60-V high voltage p-channel LDMOS devices. Here, a drain-side pnp arranged-type in a pLDMOS-SCR parasitic structure is used to investigate the layout placement effect. At first, the layout type of P+ region is continuous extended into the drain-side. Secondly, the layout type of P+ region are changed by some discrete-distributed areas into the drain-side. From TLP experimental results, we can find that the layout type of discrete-distributed type in the drain-side have a better ESD capability than the continuous extended type, then the secondary breakdown current (It2) value can be achieved above 7 A. However, the holding voltage (Vh) of the continuous extended type shows an escalating trend, so it can be having higher latch-up immunity.

Anti-ESD impacts on 60-V P-channel LDMOS devices as none-ODs zone inserting in the bulk region

For the reliability considerations, a 60-V power p-channel LDMOS transistor co-designed with none-OD zone in the bulk end by a 0.25-μm process will be evaluated in this paper. From the experimental data found that as the none-OD zones inserting, meanwhile the none-OD zone percentage was increased, the anti-ESD capability will be strengthened too, i.e. its It2 value is improved by using this manner. Nevertheless, as the none-OD zone ratio increased, the trigger voltage (Vt1) results of these samples are not changed so much, and all of the variation is in a range of 1 to 2-V. On the other hand, the on-resistance (Ron) result will be decreased, which can be considered as more even conduction. Eventually, from the TLP testing data, we can find that the anti-ESD capability (It2 value) upgraded nearly 15.4%, and on-resistance (Ron) value decreased nearly 8.6% as compared with the reference sample.

Impacts on the anti-ESD/ anti-LU immunities by the drain-side superjunction structure of HV/ LV nMOSFETs

Experimental comparisons between the reference pure sample and composite devices with a super-junction (SJ) structure in the drain-side of low-voltage and high-voltage MOSFETs are investigated in this paper. From testing results, the drain-side engineering of super-junction methodology has negative (positive) impacts on the anti-ESD capability in the LV nMOSFET (HV nLDMOS) devices. Then as a result, the layout type of nMOSFET-SJ (nLDMOS-SJ) has a lower (higher) It2 and Vh values. Eventually, it can be summarized that this drain-side SJ structure of MOSFET device is a bad (good) choice for the anti-ESD/ anti-LU robustness improvements for the LV (HV) process.

ESD-Reliability Analysis and Strategy of the GaN-Based Light-Emitting Diodes

Compounds such as GaN, ZnSe, and SiC are the compounds that currently hold the most potential in developing blue light-emitting diodes (LEDs) and blue laser diodes (LDs). Speaking of the physical property, the gallium nitride belongs to a direct bandgap material with an obviously super luminous efficiency; therefore, the gallium nitride has the dominate tendency than that of others materials. Although the gallium nitride has excellent physical properties, but in actually it is suffered many challenges during the manufacture process. Especially, it is extremely sensitive to the electrostatic discharge (ESD) threat. In other words GaN diodes generally exhibit very low anti-ESD capabilities when in HBM, MM reversed bias modes. These LEDs in the MM stress situation, its ESD immunity level usually is only about 50-V extremely low anti-ESD ability. Therefore, in this paper, GaN LED DUTs will be stressed and investigated under HBM and MM pulses bombardments, and the aim of this work is to describe a detailed investigation of the factors that limit the robustness of GaN-based LEDs under ESD transient events; finally they will provide some countermeasures in ESD reliability consideration.

Effect of Drain FODs on ESD/LU Immunities in the 60-V High-Voltage nLDMOS

Electrostatic discharge (ESD) and latch-up (LU) are the most challenging problems in high-voltage (HV) ICs due to their high power supply voltages. So, an HV LDMOS should be compromised with a high driving capability and high reliability, but it always has obvious conflicts. An MOSFET device fabricated by a multi-finger structure can’t completely turn on, which resulting in the ESD capacity per unit length is very low especially for an HV device. Then, the non-uniform turned-on phenomenon in an LDMOS is seriously impacted the ESD reliability. Therefore, a drain-side engineering is investigated in this paper, which is by adding a field-oxide-device (FOD) structure in the drain side. Does it can solve the non-uniform turned-on problem? After a systematic analysis, it is found that by adding FOD structures in the drain-side is favor to ESD capability (It2 value) in the case of high FOD/n+ ratio as the FOD/N+ area ratio is larger than 80/100. However, as compared with the original reference DUT, the Vh value is increased about 16.37 ~ 59.87 %, which allows devices more robust in the latch-up (LU) immunity.