Shayak Banerjee

Compensating non-optical effects using electrically driven optical proximity correction

Chip performance and yield are increasingly limited by systematic and random variations introduced during wafer processing. Systematic variations are layout-dependent and can be broadly classified as optical or non-optical in nature. Optical effects have their origin in the lithography process including mask, RET, and resist. Non-optical effects are layout-dependent systematic variations which originate from processes other than lithography. Some examples of nonoptical effects are stress variations, well-proximity effect, spacer thickness variations and rapid thermal anneal (RTA) variations. Semiconductor scaling has led to an increase in the complexity and impact of such effects on circuit parameters. A novel technique for dataprep called electrically-driven optical proximity correction (ED-OPC) has been previously proposed which replaces the conventional OPC objective of minimization of edge placement error (EPE) with an electrical error related cost function. The introduction of electrical objectives into the OPC flow opens up the possibility of compensating for electrical variations which do not necessarily originate from the lithographic process. In this paper, we propose to utilize ED-OPC to compensate for optical as well as non-optical effects in order to mitigate circuit-limited variability and yield. We describe the impact of non-optical effects on circuit parameters such as threshold voltage and mobility. Given accurate models to predict variability of circuit parameters, we show how EDOPC can be leveraged to compensate circuit performance for matching designer intent. Compared to existing compensation techniques such as gate length biasing and metal fills, the primary advantage of using ED-OPC is that the process of fragmentation in OPC allows greater flexibility in tuning transistor properties. The benefits of using ED-OPC to compensate for non-optical effects can be observed in reduced guard-banding, leading to less conservative designs. In addition, results show a 4% average reduction in spread in timing in compensating for intra-die threshold voltage variability, which potentially translates to mitigation of circuit-limited yield.

Electrically driven optical proximity correction

Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance. Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC, while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better timing accuracy can be achieved despite larger edge placement error.

Direct measurement of the fermi energy in graphene using a double-layer heterostructure

We describe a technique which allows a direct measurement of the relative Fermi energy in an electron system by employing a double-layer heterostructure. We illustrate this method by using a graphene double layer to probe the Fermi energy as a function of carrier density in monolayer graphene, at zero and in high magnetic fields. This technique allows us to determine the Fermi velocity, Landau level spacing, and Landau level broadening. We find that the N=0 Landau level broadening is larger by comparison to the broadening of upper and lower Landau levels.

ICCAD-2013 CAD contest in mask optimization and benchmark suite

Optical microlithography is the technique of printing a set of shapes on a wafer using light transmitted through a template called a mask. Repeatedly printing and stacking such shapes on top of each other to build electrical circuits allows us to manufacture chips in high volume. However this technique has now reached its fundamental physical limits of resolution. Current 193nm wavelength light is no longer sufficient to reliably transfer patterns which are now in the sub-100nm dimensional range. This has led to increased research in optimizing lithographic masks to pre-compensate for distortions introduced by the lithographic process. This is called mask optimization. In this contest, students are provided with a sample lithographic model which simulates the transfer of a mask pattern on to wafer. The mask is assumed to be a pixelated template, where every pixel can be turned on or off, to indicate where light passes through, or is blocked. Contestants are also provided with models to predict the robustness of their pattern i.e. how much variability is in the transferred pattern. Given these tools, the objective is to minimize the variability in the wafer image, as measured by process variability (PV) bands. This is subject to the constraints of runtime and satisfying pattern fidelity i.e. the transferred pattern should resemble the target pattern. Benchmarks are provided in the form of collections of geometric shapes, each of which provides a challenge in printing at sub-wavelength.

System-in-a-package integration of SAW RF Rx filter stacked on a transceiver chip

Demands for mobile phones with smaller form factor and lower cost have driven enhanced integration of electronics components. However, surface acoustic wave (SAW) filters must be fabricated on piezoelectric substrates, and so they are difficult to monolithically integrate on semiconductor chips. This paper reports on a compact wafer-scale packaged SAW filter stacked over a transceiver chip in a quad flat-pack no-lead (QFN) package. An integrated passive device (IPD) provided redistribution and matching between the SAW filter output and the transceiver input. Both extended global system for mobile communications (EGSM) and DCS filters were evaluated. Results demonstrated that conventional packaging techniques could be used to successfully assemble stacked SAW on transceiver modules without damage. SAW compact models based on the coupling of modes model were developed to facilitate system design. Electromagnetic simulations of coupling between SAW filters and inductors integrated on the transceiver suggested that design care is needed to avoid interactions, especially if an IPD is not used as a spacer. With appropriate design, stacked SAW filter on transceiver offers viable module integration.

Electrically driven optical proximity correction based on linear programming

Conventional optical proximity correction (OPC) tools aim to minimize edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45 nm and beyond, printing perfect polygons is practically impossible to achieve. In addition, prohibitively high mask complexity is incurred, leading to high mask cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance. Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with accurate electrical modeling of resist contours to predict the on/off current through a transistor gate. The computation of mask edge movements is cast as a linear program based on optical and electrical sensitivities. The objective is to minimize the error in saturation current between printed and target shapes. This optimization is then solved with fast runtime. The results on industrial 45 nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC. This is achieved at less than 26% runtime overheads, while also lowering mask complexity by up to 43%. The results confirm that better timing accuracy can be achieved despite larger edge placement error.

SMATO: simultaneous mask and target optimization for improving lithographic process window

Low-k1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower level metals used for local routing, where bi-directionality gives rise to lithography unfriendly layout patterns. However, one can modify such wires without significantly affecting design behavior. In this paper, we propose to simultaneously modify mask and target during OPC to improve lithographic yield. The method uses image slope information, available during image simulation at no extra cost, as a measure of process window. We derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We then develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample metal1 (M1) layouts show that the use of SMATO reduces the Process Manufacturability Index (PMI) [18] by 15.4% compared to OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared to PWOPC, we observe 4.6% improvement in PMI at large (2.6X) improvement in runtime.

Integrated model-based retargeting and optical proximity correction

Conventional resolution enhancement techniques (RET) are becoming increasingly inadequate at addressing the challenges of subwavelength lithography. In particular, features show high sensitivity to process variation in low-k1 lithography. Process variation aware RETs such as process-window OPC are becoming increasingly important to guarantee high lithographic yield, but such techniques suffer from high runtime impact. An alternative to PWOPC is to perform retargeting, which is a rule-assisted modification of target layout shapes to improve their process window. However, rule-based retargeting is not a scalable technique since rules cannot cover the entire search space of two-dimensional shape configurations, especially with technology scaling. In this paper, we propose to integrate the processes of retargeting and optical proximity correction (OPC). We utilize the normalized image log slope (NILS) metric, which is available at no extra computational cost during OPC. We use NILS to guide dynamic target modification between iterations of OPC. We utilize the NILS tagging capabilities of Calibre TCL scripting to identify fragments with low NILS. We then perform NILS binning to assign different magnitude of retargeting to different NILS bins. NILS is determined both for width, to identify regions of pinching, and space, to locate regions of potential bridging. We develop an integrated flow for 1x metal lines (M1) which exhibits lesser lithographic hotspots compared to a flow with just OPC and no retargeting. We also observe cases where hotspots that existed in the rule-based retargeting flow are fixed using our methodology. We finally also demonstrate that such a retargeting methodology does not significantly alter design properties by electrically simulating a latch layout before and after retargeting. We observe less than 1% impact on latch Clk-Q and D-Q delays post-retargeting, which makes this methodology an attractive one for use in improving shape process windows without perturbing designed values.

Methods for joint optimization of mask and design targets for improving lithographic process window

Abstract. Low-k1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower-level metals used for local routing, where bi-directionality and tight pitches give rise to lithography unfriendly layout patterns. However, there exists inherent unutilized flexibility in design shapes, e.g., one can modify such wires without significantly affecting design behavior. We develop two different techniques to simultaneously modify mask and design shapes during optical proximity correction (OPC) to improve lithographic yield of low-level metal layers. The methods utilize image slope information, which is available during OPC image simulations at no extra cost, as a measure of lithographic process window. We first propose a method that identifies fragments with low normalized image log slope (NILS) and then use this NILS information to guide dynamic target modification between iterations of OPC. The method uses a pre-characterized lookup table to assign a different magnitude of local target correction to different NILS bins. Next we develop an optimization flow where we derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample 1× (M1) layouts show that the use of SMATO reduces the process manufacturability index (PMI) by 15.4% compared with OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared with process window optical proximity correction (PWOPC), we observe 4.6% improvement in PMI at large (2.6×) improvement in runtime.

Wire delay variability in nanoscale technology and its impact on physical design

Current technology scaling trends are changing the character of wire delay variability. The distribution of wire delay is asymmetric, with a long positive tail which can be as much as 2X longer than the negative tail. This is due to the geometry of these wires, where the aspect ratio is biased towards tall thin wire cross-sections, as well as manufacturing induced variations particularly from lithography. These trends are important for timing closure, whether done via corner-based or statistical analysis. In this paper, we explore these trends, demonstrate their impact in a modern 32nm CMOS design, and suggest ways in which this trend can be managed and reduced. Particularly, through physical synthesis optimization on industrial designs, we show how these trends/observations can be utilized to produce more reliable designs. As the interconnect scaling lags behind the device scaling, the importance of wire variability will grow further in the future technology nodes.