Sheng-Yung Chen

In situ beam drift detection using a two-dimensional electron-beam position monitoring system for multiple-electron-beam–direct-write lithography

Electron-beam lithography is one of the promising candidates to replace optical projection lithography due to its high resolution and maskless direct-write capability. In order to achieve the throughput requirement for high-volume manufacturing, miniaturized electro-optics elements are utilized to drive massively parallel beams simultaneously. In high-throughput multiple-electron-beam systems, beam positioning drift problems can become quite serious due to several factors such as thermal distortion and fabrication errors of electron optics. In single-beam systems, periodic recalibration with reference markers on the wafer can be utilized to achieve beam placement accuracy. This technique is not easy for multiple-beam systems. In this article, an innovative in situ two-dimensional electron-beam position monitoring system for multiple-electron-beam lithography is studied. An array of miniaturized electron detectors to measure scattered electrons from the substrate is placed above the wafer. It is assumed that the detector array signals are correlated with the distribution of electron trajectories, and the change of trajectory distortion due to the beam drift can be predicted by Monte Carlo electron-scattering simulation. A standard quadrant detection (SQD) method and a linear least-squares (LLS) method are used to estimate the beam drift from the detector array signals. Simulation results indicate that while the estimation uncertainty of both methods can be reduced substantially when the number of detected electrons is large enough. The LLS method always outperforms the SQD one regardless the detected electron numbers.

Manufacturability Analysis of a Micro-Electro-Mechanical Systems-Based Electron-Optical System Design for Direct-Write Lithography

Multiple-electron-beam–direct-write lithography is one promising candidate for next-generation lithography because of its high resolution and ability of maskless operation. To achieve the throughput for high-volume manufacturing, miniaturized electro-optics elements are utilized to drive massively parallel beams simultaneously. Fabrication errors and uniformity of the elements can be serious issues in multiple-beam systems. Traditionally, electron optical systems (EOSs) are assembled and tested directly after the elements are fabricated. The yield by this technique can degrade significantly with multiple beams. In this work, a new EOS design-to-manufacturing flow which takes fabrication errors into account before the assembly process is proposed. The errors and imperfect components can be clearly screened by rigorous electron trajectory simulation. The effectiveness of the proposed approach is demonstrated with an fabricated electron-optical-objective-lens subject to imperfect hole profiles and substrate topography. Simulation results indicate that its EOS performances are acceptable even with significant fabrication errors.

Lithography-patterning-fidelity-aware electron-optical system design optimization

Low-energy electron beamlithography is a promising patterning solution for the 21 nm half-pitch node and beyond due to its high resolution, low substrate damage, and increased resist sensitivities. To ensure a successful electron-optical system (EOS) design, many factors such as focusing properties (FPs) and patterning fidelity (PF) have to be considered. In traditional EOSoptimization flow, FPs are typical performance indices selected when optimizing the EOS design parameters. In each numerical iteration, the EOS FP simulation results are compared with specified performance index values. The differences are reduced by adjusting the EOS design parameters until convergence. However, the performance indices related to FPs may have no direct relation to lithography PF, which is judged by the quality of the developed resist patterns. A new EOS design methodology which directly incorporates lithography PF metrics into the optimization flow is proposed. The EOS design parameters are first optimized while meeting the geometric constraints by using the traditional design flow to obtain acceptable FPs. In order to ensure lithography PF, writing patterns are selected and writing parameters are optimized. Then, constraints and cost functions related to PF are selected to further optimize the EOS design parameters to obtain acceptable PF. In each numerical iteration, the simulated lithography patterning results are compared against specified PF metric values. Their differences are reduced by adjusting the EOS design parameters until all constraints are met and PF cost functions are converged. The proposed method is applied to an EOS structure design for a 5 keV electron beamlithography system which includes a single-gate source and a focusing lens. Initial values of EOS design parameters and geometric constraints are selected based on previous studies. A drawn layout for a 22 nm isolated line pattern is used for verifying the lithography PF specifications based on the International Technology Roadmap of Semiconductors. The developed resist pattern after applying the proposed method clearly indicates that the PF is significantly improved from the value of corresponding critical dimension (CD) and the value of gate CD control.

Preliminary design of a two-dimensional electron beam position monitor system for multiple-electron-beam-direct-write lithography

Multiple-electron-beam-direct-write lithography is one of the promising candidates for next-generation lithography because of its high resolution and ability of maskless operation. In order to achieve the throughput requirement for highvolume manufacturing, miniaturized electro-optics elements are utilized in order to drive massively parallel beams simultaneously. Electron beam drift problems can become quite serious in multiple-beam systems. Periodic recalibration with reference markers on the wafer has been utilized in single-beam systems to achieve beam placement accuracy. This technique becomes impractical with multiple beams. In this work, architecture of a two dimensional beam position monitor system for multiple-electron-beam lithography is proposed. It consists of an array of miniaturized electron detectors placed above the wafer to detect backscattered electrons. The relation between beam drift and distribution of backscattered-electron trajectories is simulated by an in-house Monte Carlo electron-scattering simulator. Simulation results indicate that electron beam drift may be effectively estimated from output signals of detector array with some array signal processing to account for cross-coupling effects between beams.

New method of optimizing writing parameters in electron beam lithography systems for throughput improvement considering patterning fidelity constraints

Abstract. Low-energy electron beam lithography is one of the promising next-generation lithography technology solutions for the 21-nm half-pitch node and beyond because of fewer proximity effects, higher resist sensitivity, and less substrate damage compared with high-energy electron beam lithography. To achieve high-throughput manufacturing, low-energy electron beam lithography systems with writing parameters of larger beam size, larger grid size, and lower dosage are preferred. However, electron shot noise can significantly increase critical dimension deviation and line edge roughness. Its influence on patterning prediction accuracy becomes nonnegligible. To effectively maximize throughput while meeting patterning fidelity requirements according to the International Technology Roadmap for Semiconductors, a new method is proposed in this work that utilizes a new patterning prediction algorithm to rigorously characterize the patterning variability caused by the shot noise and a mathematical optimization algorithm to determine optimal writing parameters. The new patterning prediction algorithm can achieve a proper trade-off between computational effort and patterning prediction accuracy. Effectiveness of the new method is demonstrated on a static random-access memory circuit. The corresponding electrical performance is analyzed by using a gate-slicing technique and publicly available transistor models. Numerical results show that a significant improvement in the static noise margin can be achieved.

Fresnel Zone Plate Manufacturability Analysis for Direct-Write Lithography by Simulating Focusing and Patterning Performance versus Fabrication Errors

Zone plate array lithography (ZPAL) in the X-ray or EUV regimes is one possible next-generation lithography solution because of its potential for high-resolution and maskless operation. To achieve a high throughput, Fresnel zone plates (FZPs) are integrated to form arrays of massively parallel exposure beams. FZP fabrication errors and uniformity can be serious issues in ZPAL systems, which are usually assembled and tested directly after zone plate arrays (ZPAs) are fabricated. The yield of this approach can decrease significantly with increasing beam number. A new ZPA design-to-manufacture flow that takes fabrication errors into account before the assembly process is proposed. The errors can be clearly screened by rigorous optical and lithography simulations. The effectiveness of the proposed approach is demonstrated by analyzing preliminary FZP designs of different zone numbers subject to imperfect zone width control. Simulation results indicate that FZPs with smaller zone numbers can tolerate larger radius deviations.

Fabrication of metrology test structures with helium ion beam direct write

The availability of metrology solutions, one of the key factors to drive leading edge semiconductor devices and processes, can be confronted with difficulties in the advanced node. For developing new metrology solutions, high quality test structures fabricated at specific sizes are needed. Conventional resist-based lithography have been utilized to manufacture such samples. However, it can encounter significant resolution difficulties or requiring complicated optimization process for advanced technology node. In this work, potential of helium ion beam direct milling (HIBDM) for fabricating metrology test structures with programmed imperfection is investigated. Features down to 5 nm are resolvable without implementing any optimization method. Preliminary results have demonstrated that HIBDM can be a promising alternative to fabricate metrology test structures for advanced metrology solutions in sub 10 nm node.

Design of an electron-optical system with a ball-tip emission source through a numerical optimization method for high-throughput electron-beam–direct-write lithography

To improve the throughput of electron-beam–direct-write lithography (EBDWL), we propose a new electron-optical system (EOS) design method with the capability of systematically optimizing EOSs with various types of emission source. A ball-tip emission source initially proposed by another group is further discussed. A numerical optimization method is utilized in the design method to maximize EOS emission current while satisfying constraints including the size of the electron beam spot and the amount of induced electric field on electrodes and insulators inside EOSs. For performance comparison, two EOSs, one with a generic emission source and the other with a ball-tip emission source, are designed using the proposed method. Preliminary results indicate that a sixfold emission current is obtained from the EOS with the ball-tip emission source. Furthermore, patterning fidelity investigations are conducted using the obtained design results. It is shown that the higher emission current from the ball-tip emission source is achieved without compromising patterning quality.