Chun-Hung Liu

On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region

In this letter, on-resistance (<i>R</i> _on) degradation induced by hot-carrier injection in n-type lateral DMOS transistors with shallow-trench isolation (STI) in the drift region is investigated. <i>R</i> _on decreases at the beginning of stress, but <i>R</i> _on increases as the stress time is increased. Experimental data and technology computer-aided-design simulation results reveal that hot-hole injection and trapping at the STI corner closest to the channel are responsible for the <i>R</i> _on reduction. The damage caused by hot-electron injection at the STI edge closest to the drain is responsible for the <i>R</i> _on increase.

Effect of Drift-Region Concentration on Hot-Carrier-Induced

In this letter, hot-carrier-induced on-resistance (Ron) degradation in lateral DMOS transistors with different n-type drift-drain (NDD) region concentration is investigated. Increasing NDD concentration results in greater bulk (Ib) and gate currents (Ig), but Ron degradation is improved. Technology computer-aided design simulations reveal that high NDD concentration increases impact-ionization rate in accumulation (related to Ib increase) and channel regions (related to Ig increase) but reduces impact-ionization rate in spacer region. Charge-pumping data confirm that hot-carrier-induced interface state created in the spacer region is reduced, leading to improved Ron degradation in high-NDD-concentration device.

R_{\rm on}

Channel length (Lch) dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor (DEMOS) transistors stressed under high drain voltage and high gate voltage is investigated. On-resistance degradation is reduced in longer Lch device, however, threshold voltage shift (ΔVT) is greater. Charge pumping data reveal that electron trapping in gate oxide above channel region is responsible for ΔVT. Simulation results show that longer Lch device exhibits enhanced vertical electric field (Ey), i.e., enhanced hot-electron injection, in channel region due to the alleviation of Kirk effect. Results presented in this letter reveal that enhanced ΔVT driven by enhanced channel Ey may become a serious reliability concern in DEMOS transistors with longer Lch.

Degradation in nLDMOS Transistors

Electron-beam lithography is one of the promising candidates to replace optical projection lithography due to its high resolution and maskless direct-write capability. In order to achieve the throughput requirement for high-volume manufacturing, miniaturized electro-optics elements are utilized to drive massively parallel beams simultaneously. In high-throughput multiple-electron-beam systems, beam positioning drift problems can become quite serious due to several factors such as thermal distortion and fabrication errors of electron optics. In single-beam systems, periodic recalibration with reference markers on the wafer can be utilized to achieve beam placement accuracy. This technique is not easy for multiple-beam systems. In this article, an innovative in situ two-dimensional electron-beam position monitoring system for multiple-electron-beam lithography is studied. An array of miniaturized electron detectors to measure scattered electrons from the substrate is placed above the wafer. It is assumed that the detector array signals are correlated with the distribution of electron trajectories, and the change of trajectory distortion due to the beam drift can be predicted by Monte Carlo electron-scattering simulation. A standard quadrant detection (SQD) method and a linear least-squares (LLS) method are used to estimate the beam drift from the detector array signals. Simulation results indicate that while the estimation uncertainty of both methods can be reduced substantially when the number of detected electrons is large enough. The LLS method always outperforms the SQD one regardless the detected electron numbers.

Channel length dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor transistors

A model-based proximity effect correction methodology is proposed and tested for electron-beam-direct-write lithography. It iteratively modulates layout geometry by feedback compensation until the correction error converges. The energy intensity distribution is efficiently calculated by fast convolving the modulated layout with a point-spread function which models electron beam shape and proximity effects primarily due to electron scattering in resist. The effectiveness of this methodology is measured by iteration numbers required for meeting the patterning fidelity specifications. It is examined versus process parameters including acceleration voltage and resist thickness with several regular mask geometries and practical design layouts.

In situ beam drift detection using a two-dimensional electron-beam position monitoring system for multiple-electron-beam–direct-write lithography

Accelerating voltage as low as 5 kV for operation of the electron-beam micro-columns as well as solving the throughput problem is being considered for high-throughput direct-write lithography for the 22-nm half-pitch node and beyond. The development of efficient proximity effect correction (PEC) techniques at low-voltage is essential to the overall technology. For realization of this approach, a thorough understanding of electron scattering in solids, as well as precise data for fitting energy intensity distribution in the resist are needed. Although electron scattering has been intensively studied, we found that the conventional gradient based curve-fitting algorithms, merit functions, and performance index (PI) of the quality of the fit were not a well posed procedure from simulation results. Therefore, we proposed a new fitting procedure adopting a direct search fitting algorithm with a novel merit function. This procedure can effectively mitigate the difficulty of conventional gradient based curve-fitting algorithm. It is less sensitive to the choice of the trial parameters. It also avoids numerical problems and reduces fitting errors. We also proposed a new PI to better describe the quality of the fit than the conventional chi-square PI. An interesting result from applying the proposed procedure showed that the expression of absorbed electron energy density in 5keV cannot be well represented by conventional multi-Gaussian models. Preliminary simulation shows that a combination of a single Gaussian and double exponential functions can better represent low-voltage electron scattering.

Model-based proximity effect correction for electron-beam direct-write lithography

The mechanism of hot-carrier-induced degradation in n-type lateral diffused metal-oxide-semiconductor (LDMOS) transistors is investigated. Experimental data reveal that hot-electron injection induced interface state generation in channel region is the main degradation mechanism. Since gate current (Ig) consists mainly of electron injection, Ig correlates well with device degradation. As a result, a lifetime prediction method based on Ig is presented for the purpose of projecting hot-carrier lifetime in LDMOS transistors.

A novel curve-fitting procedure for determining proximity effect parameters in electron beam lithography

Electron-beam-direct-write lithography has been considered a candidate next-generation technique for achieving high resolution. An accurate point spread function (PSF) is essential for reliable patterning prediction and proximity-effects correction. It can be derived via an effective parametric PSF calibration methodology, typically involving the fitting of the absorbed energy distribution (AED) from an electron-scattering simulation. However, the existing parametric PSF calibration methodology does not employ a systematic approach to obtain a new PSF form that is both compact and accurate when conventional PSF forms are not satisfactory. Only the AED fitting quality (rather than its patterning-prediction quality) is considered during the conventional calibration methodology. It also lacks a process to consider whether the predicted deviation (as simulated using the chosen PSF form) is satisfactory. This paper proposes a new parametric PSF calibration methodology to systematically obtain a PSF form consisting of the smallest number of terms, with a better combination of basis functions and that optimizes pattern accuracy. The effectiveness of using the new methodology is demonstrated in terms of fitting accuracy, patterning-prediction accuracy, and patterning sensitivity.

Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors

Electron-beam–direct-write lithography at lower accelerating voltages has been considered as a candidate for next-generation lithography. Although long-range proximity effects are substantially reduced with the voltage, proximity effect correction (PEC) is still necessary since short-range proximity effects are relatively prominent. The effectiveness of model-based PEC can be limited severely if an inaccurate point spread function (PSF) characterizing electron scattering within resist is adopted. Recently, a new PSF form using a promising calibration method has been developed to more accurately characterize the electron scattering and thus significantly improve patterning fidelity at 5u2009keV. However, influences of adopting the conventional and new PSF forms for the usage of patterning practical circuit layouts have not been intensively studied. This work extensively investigates impacts of PSF accuracy on patterning prediction and PEC under different resist thickness conditions suitable for various lithogr...

New parametric point spread function calibration methodology for improving the accuracy of patterning prediction in electron-beam lithography

The mechanisms of hot-carrier-induced linear drain current (Idlin) degradation in a 0.35μm n-type lateral diffused metal-oxide-semiconductor transistor, operating at a nominal voltage of 12V, is investigated. Results and analysis show that the location of hot-carrier-induced interface states varies with stress gate voltage. Stress-induced interface states located in accumulation region under polygate have little effect on Idlin degradation. As a result, interface states located in drain-side spacer region dominate Idlin degradation when interface states located in channel region are negligible.