Jinian Bian

Integrating dynamic thermal via planning with 3D floorplanning algorithm

Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the thermal resistances between device layers. In this paper, we integrate dynamic thermal via planning into 3D floorplanning process. Our 3D floorplanning and thermal via planning approaches are implemented in a two-stage approach. Before floorplanning, the temperature-constrained vertical thermal via planning is formulated as a convex programming problem. Based on the analytical solution, blocks are assigned into different layers by solving a sequence of knapsack problems. Then a SA engine is used to generate floorplans of all these layers simultaneously. During floorplanning, thermal vias are distributed horizontally in each layer with white space redistribution to optimize thermal via insertion. Experimental results show that compared to a recent published result from [14], our method can reduce thermal vias by 15% with 38% runtime overhead.

UNISM: Unified Scheduling and Mapping for General Networks on Chip

Task scheduling and core mapping have a significant impact on the overall performance of network on chip (NOC). In this paper, a unified task scheduling and core mapping algorithm called UNISM is proposed for different NOC architectures including regular mesh, irregular mesh and custom networks. First, a unified model combining scheduling and mapping is introduced using mixed integer linear programming (MILP). Then, a novel graph model is proposed to consider the network irregularity and estimate communication energy and latency, since the number of network hops is not accurate enough for irregular mesh and custom networks. To make the MILP-based UNISM scalable, a heuristic is employed to speed up our method. Compared with two previous state-of-the-art works, experimental results show that more than 15% and 11.5% improvement on the execution time is achieved with similar energy consumption on average for regular mesh NOC. For irregular and custom NOC, the improvement is 27.3% and 14.5% on the execution time with 24.3% and 18.5% lower energy. Moreover, our method is scalable for large benchmarks in terms of runtime.

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.

A novel fixed-outline floorplanner with zero deadspace for hierarchical design

Fixed-outline floorplanning, which enables hierarchical design, is considered more and more important nowadays. In this paper, a novel SA-based Fixed-outline Floorplanner with the Optimal Area utilization named SAFFOA is introduced to improve the total wirelength. The basic idea is to build and solve a group of four quadratic equations in four variables iteratively, which can handle the fixed-outline constraint of any aspect ratio. A new topological representation called Ordered Quadtree is then custom-made for this basic idea to facilitate its integration into SA iterations. After the fixed-outline constraint with 100% area utilization is achieved, we will solve the tradeoff between the chip area and wirelength and thus concentrate on the latter in SA process. Experimental results show that the chip wirelength is decreased by about 16.8% and 8.6% on average, compared with two previous fixed-outline floorplanners on soft modules, which are both proved to be better than Parquet. Besides, our method is still competitive on the wirelength, even if compared with some leading-edge outline-free floorplanners. At last, Local Refinement is also adopted to guide the SA process and reshape soft modules to meet the constraint on their aspect ratios (ARs). With its help, SAFFOA can still generate feasible floorplans with no deadspace under a strict AR constraint such as [0.5,2].

FSM decomposition for power gating design automation in sequential circuits

Power gating is one of the most effective techniques for low power design because it reduces both dynamic and static power simultaneously. This paper proposes a circuit architecture to implement power gating in sequential circuits based on finite state machine (FSM) decomposition, which is implemented by partition the state transition graph (STG). The FSM is partitioned into two or more sub-machines, only one of which is active most of the time, and the power supply of other sub-machines can be cut off to save energy. Since adjustment of supply voltage may not finish instantly, the voltage of the submachine that will be activated need to be raised ahead of time, which makes the problem complicated. We propose a simulated annealing algorithm to perform the decomposition without timing penalty. Experimental results have shown the effectiveness of our approach, and it is expected that power gating will show superior power saving to clock gating due to the increasing significance of static power.

EHSAT: an efficient RTL satisfiability solver using an extended DPLL procedure

This paper presents an efficient algorithm to solve the satisfiability (SAT) problem for RTL designs using a complete hybrid branch-and-bound strategy with conflict-driven learning. The main framework is the extended Davis-Putnam-Logemann-Loveland procedure (DPLL) which is a unified procedure combining Boolean logic and arithmetic operations. A hybrid two- literal-watching scheme and interval reasoning based on RTL predicates are used as the powerful hybrid constraint propagation strategies. Conflict-based learning is also implemented as another important technique to enhance efficiency. Comparisons with a state-of-the-art RTL SAT solver, a SMT solver and an ILP solver show that EHSAT outperforms these solvers for RTL satisfiability problems.

ISBA: an independent set-based algorithm for automated partial reconfiguration module generation

Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in current DPR design flow, leveraging these benefits requires specific designer expertise with laborious manual design effort. Considering the complicated concurrency relations among functions, it is challenging to properly select Partial Reconfiguration Modules (PR Modules) and partition them into groups so that the hardware modules can be swapped in and out during the run time. Whats more, the design of PR Modules also impacts reconfiguration latency and resource utilization greatly. In this paper, we formulate the PR Module generation problem into a standard Maximum-Weight Independent Set Problem (MWISP) so that the original manual exploration can be solved optimally and automatically. Our proposed algorithm not only supports various design constraints, but also has the ability to consider multiple objectives such as area and reconfiguration delay. Experimental results show that our approach can optimize resource utilization and reduce reconfiguration delay with good scalability. Especially, the implementation of the real design case shows that our approach can be embedded in the Xilinxs DPR design flow successfully and it can save around 70% reconfiguration latency overhead compared with the heuristic PR Module generation approaches.

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation

An efficient and effective divide-and conquer 2.5D floorplanning algorithm is proposed for wirelength optimization. Modules are pre-partitioned into different dies with respect to the statistical wirelength estimation result. Then a floorplan is generated on each die for wirelength optimization. The new partitioning method successfully solves the conflict between wirelength minimization and inter-die via constraints. Experimental results show that our algorithm could provide noticeable improvement in the total wirelength compared to both 2D design and the previous 2.5D floorplanning algorithm.

A hierarchical CDFG as intermediate representation for hardware/software codesign

A hierarchical CDFG model designed as an intermediate representation for hardware/software (HW/SW) codesign is presented in this paper. A new concept of transport node, which represents the communication resources of the system, is proposed in this model. Hierarchical feature can be straightly obtained through extending the definition of nodes, allowing them to nest sub-CDFG recursively. Then it is demonstrated how to build basic control constructs of branches and loops. Explaining in a short introduction to the translation process, such a hierarchical CDFG is suitable for HW/SW codesign as an intermediate representation. The hierarchical CDFG model can capture the design information from source file specified by VHDL or C language. It maintains relative simplicity while providing helpful features for HW/SW partitioning and High-level synthesis tools.