Sherif Sweha

A multilevel-cell 32 Mb flash memory

A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16 M flash memory cells. This 32 Mb flash memory on a 0.6 /spl mu/m process has a 2.0/spl times/1.8 /spl mu/m/sup 2/ flash cell. In MLC operation, the logical flash memory cell achieves two bits per cell using four possible states, defined by four flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the flash memory cell and the corresponding logic levels is shown in this paper, which also shows a plot of the four threshold voltage distributions, each with a separation range.

A 3.3V 50MHz synchronous 16Mb flash memory

A 3.3 V 50 MHz synchronous 16 Mb flash memory serves applications where zero-wait-state direct execution is essential in removing the performance bottleneck attributed to slow memory in performance (/spl ges/25 MHz) systems. This 16 Mb flash chip supports continuous burst cycles for code execution, eliminating costly code shadowing from slow nonvolatile memory to DRAM, resulting in improved system performance and lower cost. Architecture and circuit innovations give 20 ns continuous burst and a maximum data transfer rate of 100 MB/s, resulting in a greater than 3/spl times/ performance improvement over previous 16 Mb devices.

A 3.3 V 16 Mbit DRAM-compatible flash memory

A new 16 Mb (1 Mbit/spl times/16) flash memory on a 0.6 /spl mu/m CMOS process has been designed, that combines the high-speed code execution capabilities of DRAM with nonvolatile, high-density, updatable code storage of flash memory, thus replacing the traditional redundant memory paradigm with one cost-effective solution. This solution eliminates the need to shadow code from nonvolatile memory to DRAM, thus enabling design of direct-execute code and mass storage memory systems, while the fully DRAM-compatible interface allows glueless design with existing DRAM controllers.