Johnny Javanifard

A multilevel-cell 32 Mb flash memory

A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16 M flash memory cells. This 32 Mb flash memory on a 0.6 /spl mu/m process has a 2.0/spl times/1.8 /spl mu/m/sup 2/ flash cell. In MLC operation, the logical flash memory cell achieves two bits per cell using four possible states, defined by four flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the flash memory cell and the corresponding logic levels is shown in this paper, which also shows a plot of the four threshold voltage distributions, each with a separation range.

A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed

Advancing to 45 nm 1 Gb NOR flash requires new process and design techniques. The process developments of SACS, tungsten source rail, and better pump capacitors increase cell size and reduce overall die size. The design techniques of two-transistor row decoders, a new sensing architecture, more effective charge pumps and program performance improvements enable multilevel flash cells to meet a die size of 30 mm2 and 5 MB/s program speed in 45 nm technology.

A 3.3V 50MHz synchronous 16Mb flash memory

A 3.3 V 50 MHz synchronous 16 Mb flash memory serves applications where zero-wait-state direct execution is essential in removing the performance bottleneck attributed to slow memory in performance (/spl ges/25 MHz) systems. This 16 Mb flash chip supports continuous burst cycles for code execution, eliminating costly code shadowing from slow nonvolatile memory to DRAM, resulting in improved system performance and lower cost. Architecture and circuit innovations give 20 ns continuous burst and a maximum data transfer rate of 100 MB/s, resulting in a greater than 3/spl times/ performance improvement over previous 16 Mb devices.

A 128 Mb NOR flash memory with 3 MB/s program time and low-power write performance by using in-package inductor charge-pump

Improved performance of flash memories requires programming more cells in parallel. This design uses an inductive pump to transfer the energy to a capacitor to achieve the needed voltage. The discrete inductor is bonded atop the die which also includes the control circuitry. With an inductive pump, the current saving in the program mode is 47.5 mA compared to a capacitive pump.