Shi-Hao Chen

Experiences of low power design implementation and verification

In this paper, we present the experiences of some low power solutions that have been successfully implemented in 90 nm/65 nm production tape-outs. We also focus on power gating design, an effective low leakage solution, and present the experiences of power switch planning, optimization, and verification. Dynamic IR drop is an important issue in low power design, which may reduce the logic gate noise margins and result in functional or timing failures. We will present a low cost but effective methodology for dynamic IR drop prevention and fixing.

Power-Up Sequence Control for MTCMOS Designs

Power gating is effective for reducing standby leakage power as multi-threshold CMOS (MTCMOS) designs have become popular in the industry. However, a large inrush current and dynamic IR drop may occur when a circuit domain is powered up with MTCMOS switches. This could in turn lead to improper circuit operation. We propose a novel framework for generating a proper power-up sequence of the switches to control the inrush current of a power-gated domain while minimizing the power-up time and reducing the dynamic IR drop of the active domains. We also propose a configurable domino-delay circuit for implementing the sequence. Experimental results based on state-of-the-art industrial designs demonstrate the effectiveness of the proposed framework in limiting the inrush current, minimizing the power-up time, and reducing the dynamic IR drop. Results further confirm the efficiency of the framework in handling large-scale designs with more than 80 K power switches and 100 M transistors.

Electron emitters synthesized by selected area deposition of carbon nanotubes on silicon substrates

Abstract We have successfully attained patterned carbon nanotubes grown on two-dimensional Ni arrays of square blocks of various sizes on Si by a microwave-heated chemical vapor deposition process. The Ni blocks are either freestanding or isolated by the silicon dioxide. For patterned carbon nanotube emitters, grown on freestanding Ni blocks, the emission current–density increases with the size of the Ni blocks. To the contrary, patterned carbon nanotube emitters grown on 2 μm by 2 μm Ni blocks isolated by the silicon diode have exhibited an emission behavior as excellent as the un-patterned emitters; both emitters have very low turn-on and threshold fields being at ∼0.1 V/μm and ∼1.50 V/μm, respectively and can emit current density exceeding 120 mA/cm2.

DFM/DFY practices during physical designs for timing, signal integrity, and power

We present our experience of DFM (design for manufacturability) and DFY (design for yield) considerations on physical designs at 0.13 mum and below technology nodes. The impact of some DFM approaches on timing and signal integrity are addressed. We also present our experience of yield analysis and improvement for the designs with process variation and dynamic IR drop issues.

Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators

This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chips maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel built-in self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip.

Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs

Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce ICs leakage power consumption by turning off idle devices with MTCMOS power switches. In this paper, we study the usage of coarse-grain MTCMOS power switches for both logic circuits and SRAMs, and then propose corresponding methods of testing stuck-open power switches for each of them. For logic circuits, a specialized ATPG framework is proposed to generate a longest possible robust test while creating as many effective transitions in the switch-centered region as possible. For SRAMs, a novel test algorithm is proposed to exercise the worst-case power consumption and performance when stuck-open power switches exist. The experimental results based on an industrial MTCMOS technology demonstrate the advantage of our proposed testing methods on detecting stuck-open power switches for both logic circuits and SRAMs, when compared to conventional testing methods.

Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer

This paper presents a novel framework to efficiently and effectively build a robust but routing-friendly multilayer power network under the IR-drop and electro-migration (EM) constraints. The proposed framework first considers the impact of the aluminum-pad layer and provides a conservative analytical model to determine the total metal width for each power layer that can meet the IR-drop and EM constraints. Then the proposed framework can identify an optimal irredundant stripe width by considering the number of occupied routing tracks and the potential routing detour caused by the power stripes without the information of cell placement. Next, after the cell placement is done, the proposed framework applies a dynamic-programming approach to further reduce the potential routing detour by relocating the power stripes. A series of experiments are conducted based on a 40 nm, 1.1 V, and 900-MHz microprocessor to validate the effectiveness and efficiency of the proposed framework.

Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs

This paper presents a switch-routing framework which can generate a feasible Hamiltonian-path switch routing while minimizing the dynamic IR drop of a targeted fragile active domain with an analytical model. The accuracy of the analytical model and the effectiveness of the proposed framework are validated through an advanced multi-domain mobile-phone MTCMOS design.

Testing retention flip-flops in power-gated designs

This paper focuses on tackling two problems on testing retention flip-flops in power-gated designs. The first one is how to reduce the virtual-VDD discharge time after entering the sleep mode. The second one is how to avoid the test escape caused by the unintended initial value of the retention flip-flop during the restore function. To solve the first problem, we propose a novel ATPG framework to generate repeatedly toggling pattern pairs that can create maximal virtual-VDD drop for a cycle. To solve the second problem, we propose a new test procedure to avoid the unintended initial value of the retention flip-flop after restoring. The effectiveness of the proposed ATPG framework and the new test procedure will be validated through SPICE simulation based on an industrial MTCMOS cell library.

Routability-driven bump assignment for chip-package co-design

In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and substrate routing (100% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and substrate routing in a short time, while the traditional co-design flow requires weeks even months.