Jijun Ma

A Novel Approach for Finding Candidate Locations for Online FPGA Placement

Reconfigurable computing (RC) has been viewed as an efficient solution to achieve high performance and flexibility. Hardware tasks can be dynamically placed on and removed from reconfigurable platforms. Field-programmable gate arrays (FPGA) provide partially runtime reconfiguration (PRTR) at runtime. However, this reconfiguration will lead to more time overhead. An efficient algorithm to manage empty space is necessary for online task placement on a PRTR FPGA. This paper first proposes a data structure to maintain information about the available free area and then presents a novel approach to find candidate locations for online FPGA placement. Experimental results show that the approach proposed here is better than similar approaches to find locations for task placement.

Adjust ELF Format for Multi-core Architecture

There are two problems emerged while multi-core platform become popular in daily life, no matter for high end or low end. The first is how to fully utilize computing resource of these cores without requirement of large modifications of current software design model. The second is about dividing a piece of serial program into parallel program. However, the latter is the responsibility of compiler, which involves complex analysis of logical relationship and data dependency hidden in source code. Assuming a powerful compiler, we propose a new ELF format with multiple text sections each of which corresponds to a piece of logically separated code that could be loaded into a single thread. Similar research has been done on this, but they need a compiler with multiple thread library support which may lead to an overstaffed compiler. We assign this work to program loader and thus reduce design complexity of compiler.

Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications

The progress of manufacturing technology makes the integration of many cores on a single silica substrate possible, which is called chip multiprocessor (CMP). But how to design the fabric on chip is still in discussion. Based on the advantages of scalability, network on chip (NoC) is a promising solution to solve the on-chip interconnection problem. However, it is still a challenge when communications through wires dominate the performance. The network communications infrastructure (routing, adapters and wires, etc.) cost too much both in power consumption and die area. In this paper, we propose a novel on-chip structure with dynamic reconfiguration capability for I/O supported parallel application. Our motivation is to reduce the cost of chip areas greatly by dynamic reconfiguration of the network in NoC architecture under the conditions that I/O parallel applications can be supported and the performance can be optimized. In our design, I/O node will be obtained firstly and then the information of the spare processing elements (PE) near it. Finally, combined with the communication pattern of applications, wires will be reallocated and reconfigurated to create a virtual regionalized area. The experimental results show that we can get a certain level of optimization among chip area, communication efficiency and the performance of I/O supported parallel applications.

Dual OS Support Peripheral Device Encapsulation

The need of extensive computing capacity is expanding all the time. Especially in company providing network service, adding servers physically requires much more cost. Also in embedded system, resource is also very limited. That is why virtulization is so popular in research and industry application. A lot of virtulization technique is raised to supply great computing capacity with multiple operating system running synchronously in a single real machine. Of all the aspects affecting real time performance of a computer, I/O processing has played a major role. Because I/O bound process has to wait for device to be free and thus increase response time which may delay them go beyond deadline. The system-on-a-chip technology provides the scratch-pad memory(SPM), which is small, isolated and located on chip. We implement a little operating system running in SPM (SPMOS). The SPMOS provide virtual I/O interface for general operating system. Different I/O requestis buffered and scheduled if necessary. Also, with proper memory checking mechanism, we could prevent malicious attacks on SPM, which means that any program running in the SPM could be protected effectively. Experiment shows that the SPMOS based virtual I/O interface is efficient and practical.

A Virus Detection Framework based on SPMOS

Embedded systems have been used in many different areas in which sensitive information communication and storage are needed. This makes security a serious concern in embedded system design, especially in operating system design. At the same time computer virus has been mutating and developing as fast as the upgrading speed of embedded operating system. Even it is possible for some intelligent virus to destroy the anti-virus software process in the memory. The system-on-a-chip technology provides Scratch-Pad Memory(SPM) which is physically isolated with main memory and more efficient than other kind of memories. We construct a demilitarized zone(DMZ) on SPM and design a small OS named SPMOS in the DMZ. A watchdog is contained in GPOS to monitor the events occurred. If an abnormal event is detected, GPOS will trap itself to SPMOS which will invoke anti-virus program. It is a big challenge to switch the two OSes without any virtual layer support. The way to protect SPM showed that the anti-virus detection platform based on SPMOS is secure. Then the experiment results show that the platform is efficient while switching between OSes.

SPMOS-Based Intrusion Detection Architecture

Security of embedded systems is becoming more and more important. IDS (instrusion detection system) has been designed to protect systems from being compromised by network attacks. A lot of researches have been done on it. However, most of them focus on complex and time-consuming detection methods to improve accuracy of the system, with assumption that IDS is running under control of general purpose operating systems (GPOS). In this way, the IDS itself will depress overall performance and cannot be guaranteed secure. In this paper, we present an embedded architecture of SPMOS-based IDS. SPMOS, located in SPM, is a little OS running under GPOS. Experiment results show that the architecture is fast. Based on this, we also design a simple IDS and conduct tests by integrating it into SPMOS and GPOS. The former consumes the latters 8.3% time only, with less than 6.2% overhead, which verifies the architecture proposed is practical and efficient.