Shianling Wu

VirtualScan: a new compressed scan technology for test cost reduction

This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

The quality of at-speed testing is being severely challenged by the problem that an inter-clock logic block existing between two synchronous clocks is not efficiently tested or totally ignored due to complex test control. This paper addresses the problem with a novel inter-clock at-speed test control scheme, featuring a compact and robust on-chip inter-clock enable generator design. The new scheme can generate inter-clock at-speed test clocks from PLLs, and is feasible for both ATE-based scan testing and logic BIST. Successful applications to industrial circuits have proven its effectiveness in improving the quality of at-speed testing

At-speed logic BIST architecture for multi-clock designs

This paper presents an at-speed logic BIST architecture for testing multi-clock, multi-frequency designs. The scheme employed allows true at-speed test quality for circuits containing multiple clocks without any clock frequency manipulation. Physical implementation is easily achieved due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements. Application results for two industrial designs are also reported.

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction

This paper describes time-division demultiplexing and multiplexing of high-data-rate scan patterns applied on I/Os into low-data-rate scan patterns applied on VirtualScan compression circuitry to further reduce test application time and test pin-count without coverage loss

An efficient BIST method for small buffers

In this work, we propose a new built-in self-testing (BIST) method that is able to concurrently test a set of spatially distributed embedded-memory modules with different sizes. By allowing some redundant read/write operations for small modules, we develop a new march algorithm, called RSMarch, that can concurrently test all memory modules with the same fault coverage as if each module is tested individually. We also show that this method requires only one simple BIST controller and one test data line for all modules. Thus the new method has the advantages of short test time, high fault coverage and low area overhead.

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains

This paper presents a new at-speed logic built-in self-test (BIST) architecture using staggered launch-on-shift (LOS) for testing a scan-based BIST design containing asynchronous clock domains. The proposed approach can detect inter-clock-domain structural faults and intra-clock-domain delay and structural faults in the BIST design. This solves the long-standing problem of using the conventional one-hot LOS approach that requires testing one clock domain at a time which causes long test time or using the simultaneous LOS approach that requires adding capture-disabled circuitry to normal functional paths across interacting clock domains which causes fault coverage loss. Given a fixed number of BIST patterns, experimental results showed that the proposed staggered clocking scheme can detect more faults than one-hot clocking and simultaneous clocking.

Logic BIST Architecture for System-Level Test and Diagnosis

This paper describes the logic built-in self-test (BIST) architecture for test and diagnosis of ASIC devices at the system level. The proposed architecture supports the at speed staggered launch-on-capture clocking scheme and includes novel features to further increase the device’s defect coverage, place-and-route ability, ease of debug and diagnosis, and reduce test power consumption. These features include equivalent clock merging for routing considerations, programmable shift modes for overheat considerations, configurable capture modes for yield loss and IR-drop considerations, as well as BIST signature diagnosis, masked-chain diagnosis, and one-chain diagnosis at the system level. Experimental results have successfully demonstrated the feasibility of using the proposed features for system-level test and diagnosis.

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

This paper describes a core-based test and diagnosis integration and automation system, called Turbo1500, which automatically synthesizes test and diagnosis logic in accordance with the IEEE 1500 standard. Turbo1500 serves two major purposes. One is for use as a core test automation tool in a system-on-chip (SOC) environment to automatically connect multiple cores from various sources and create testbenches each targeting an individual core under the control of a chip-level test access port (TAP) controller. The other is for hierarchical (block-by-block) core test and diagnosis when chips on a printed-circuit board are embedded with 1149.1 boundary scan I/O cells and cores under test and diagnosis are surrounded with 1500-compliant wrapper cells. Application experience showed that the simplicity of the IEEE 1500 standard combined with an easy-to-use automation tool can make core-based design for test and diagnosis no longer a nightmare, especially when some cores are extremely large or complex.

At-Speed Logic BIST for IP Cores

This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.