Shibaji Banerjee

CryptoScan: A Secured Scan Chain Architecture

Scan based testing is a powerful and popular test technique. However the scan chain can be used by an attacker to decipher the cryptogram. The present paper shows such a side-channel attack on LFSR-based stream ciphers using scan chains. The paper subsequently discusses a strategy to build the scan chains in a tree based pattern with a selfchecking compactor. It has been shown that such a structure prevents such scan based attacks but does not compromise on fault coverage.

Design, fabrication, testing and simulation of porous silicon based smart MEMS pressure sensor

Porous silicon based piezoresistive pressure sensor has been designed, fabricated and tested in the range of 0 to 1 bar and temperature range of 20/spl deg/C to 80/spl deg/C. A suitable signal conditioning analog circuit consisting of constant current generator and an offset adjustable low noise instrumentation amplifier has been designed and tested. The analog output is then digitized through an ADC and fed to FPGA. Architecture for compensation of nonlinear temperature dependence of pressure sensor has been implemented and tested in FPGA. A device model of porous silicon pressure sensor has also been developed with a view to realize a SMART pressure sensor.

A 10-bit 80-MSPS 2.5-V 27.65-mW 0.185-mm/sup 2/ segmented current steering CMOS DAC

This paper presents a 10 bits 80 MSPS 2.5 V digital-to-analog converter (DAC) using 0.25 micrometer double poly four metal CMOS technology for mixed-signal applications. A segmented current steering architecture is used for this DAC. This architecture gives the most optimized results in terms of speed, resolution, area and power. The DAC can operate at a frequency of 80MHz and above. Total power dissipation is 27.6525 mW with 2.5 V power supply. It achieves differential nonlinearity and integral nonlinearity of /spl plusmn/0.55 LSB and /spl plusmn/0.4 LSB. It occupies an area of 0.185 mm/sup 2/.

Built-in self-test for flash memory embedded in SoC

Flash memories are a type of nonvolatile memory, which are becoming more and more popular for system-on-chip. But, flash memories are suffered by different types of disturb faults. In the present paper, some new disturb faults that may appear in flash memory are proposed. A modifies March algorithm is developed to detect these faults. Finally, an embedded processor-based built-in self-test (BIST) design is implemented for embedded memories. The proposed method utilizes the concept of reusing the processor in SoC environment. By reusing the embedded processor, the area overhead due to BIST can be reduced to a great extent. The area overhead is only due to the circuits required to design memory wrapper cell. The experimental results show that the area overhead due to BIST is less than 1% for a typical 256K flash memory

A programmable built-in self-test for embedded DRAMs

A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a built-in self-test (BIST) architecture is proposed with low area overhead. The test pattern generator (TPG) for generating all patterns for NPSFs is implemented with on-chip cellular automata (CA) based circuit.

Automatic generated built-in-self-test for embedded memory

Embedded memory test is becoming an important issue in system-on-chip (SOC) development. Direct access of memory cores from the limited number of I/O pins is usually not feasible. Built-in-self-test (BIST) is rapidly becoming the most acceptable solution. A BIST design for embedded DRAMs is proposed. The BIST circuit is on-line programmable for its NPSF test algorithms. Experimental results show that the present BIST design is cost effective.

Analysis of temperature dependence of Si-Ge HBT

In this paper the dependence of characteristics of SiGe heterojunction bipolar transistors on Ge mole-fraction and also variation of gain with temperature are presented. The simulation is carried out using a two dimensional device simulator, BISOF, based on finite element method. It is observed that the current gain of graded HBT improves when the temperature falls from 300 K to 200 K which matches well with the available experimental results.

A Programmable Built-in Self-Test for Embedded Memory Cores

Abstract A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a programmable BIST architecture is designed. The BIST circuit allows the users to select a vast variety of test algorithms based on their choice. The single BIST circuit is capable of testing different types of memory cores embedded in SOC. The proposed BIST circuit is shared among the different memory cores in an SOC. For this purpose, test wrappers for the shared BIST circuits and the memory cores are designed. Finally, a test scheduling algorithm is developed to reduce the overall test time.

Best repair: an efficient reconfiguration for RRAM

Reconfiguration of memory arrays with spare rows and columns has been shown to be NP-complete problem. The present paper develops a novel heuristic algorithm which solves the reconfiguration problem. The conventional technique to find the vertex cover using maximum degree has been modified using an additional step to search first for the vertices of degree one. The new heuristic algorithm found to offer a better solution in repairing the memory faults in cases where some of the existing algorithms have failed. The performance has been evaluated using extensive experimentation and probabilistic approach based on a random graph model.