Shigekazu Yamada

A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme

A 1.8 V-only 32 Mb NOR flash EEPROM uses a channel-erasing scheme for the 0.49 /spl mu/m/sup 2/ cell in 0.25 /spl mu/m CMOS technology. The block decoder circuit with an erase-reset sequence performs channel-erase. The bit line direct sense permits sub-1.8 V operation, suitable for use in handheld systems.A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory

A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3-5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2.

A 172mm 2 32Gb MLC NAND flash memory in 34nm CMOS

As applications for NAND continue to grow and cost remains a primary market driver, it is necessary to deliver increased storage capacities at smaller process lithography while meeting high performance requirements [1,2]. Design plays a pivotal role by providing architectures and design solutions that minimize the impact of bitline and wordline resistance and capacitance (RC) requirements and cell-reliability constraints. This paper presents a device that employs chip architecture, datapath, and analog architecture solutions that address these challenges while meeting high performance requirements. This 32Gb MLC NAND delivers 50µs tREAD, 900µs tPROG and 9MB/s write throughput in a 34nm technology.

A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories

A word-line voltage generator is proposed to compensate temperature variations in the threshold voltages of flash memory cells by mixing a first current with a negative temperature coefficient with a second current with zero temperature dependency whose current is adjustable per level per operation. The measured results showed that 1) the output voltage could be adjusted from 0.15V to 2.5V with a resolution of 10mV at 90C, and 2) the temperature coefficient could be adjusted from 0 to −5mV/K with a resolution of −0.04mV/K. Thus, a temperature variation in Vt of the memory cells can be reduced to ±10% with the generator circuit. The generator consumed 500μA and occupied 0.24mm2.