Shigeo Kuboki

Nonlinearity analysis of resistor string A/D converters

A mismatch in the resistor ratio causes nonlinearity in successive-approximation A/D converters fabricated with a 2^{n}R potentiometric technique. This paper describes a theoretical analysis of this kind of nonlinearity and a method of evaluating the variations in resistance obtained in experiments with monolithic resistors. The resistance variations are classified into a statistically random variation component and a deterministic variation component. The relationship of both components to the nonlinearity error is then clarified. A 7-bit diffused resistor string was fabricated with a silicon-gate NMOS process. An autocorrelation technique was used to identify and separate several resistance variation components in the string. On the basis of the theoretical and experimental results that were obtained, we have developed 10-bit A/D converters and confirmed their accuracy.

A 4K CMOS gate array with automatically generated test circuits

A 2-/spl mu/m CMOS 4K-gate array using a newly devised scan bus method has been developed. This method is applied to the array by using a double-latch structure, parallel scanning, and normal-test common pin techniques. The gate array can be tested for 95-100% of all DC faults using computer-generated test circuits and test data, without placing restrictions on the logic design. Due to an access-to-output flip-flop structure and a gate-isolated three-input type basic cell, including embedded transistors, the area increase and operating speed degradation due to test circuits are considerably reduced. Furthermore, besides the flip-flop blocks, a built-in RAM macroblock is available. Degradation of operating speed is evaluated as 10%. The scan operation is done at a clock cycle of 120 ns, and the access time of the RAM macroblock is 34 ns. The gate array includes 4032 three-input gates on a 7.2/spl times/7.02-mm chip.