Shih-Chien Liu

GaN MIS-HEMTs With Nitrogen Passivation for Power Device Applications

A GaN MIS-HEMT with nitrogen (N)-passivation for power device applications is demonstrated. In this letter, nitrogen radicals were adopted to recover nitrogen-vacancy-related defects which were formed due to the thermal decomposition and evaporation of nitrogen atoms from GaN surface during high-temperature process. Besides, nitrogen radicals can also remove impurities and reduce surface dangling bonds by forming Ga-N bonds on the SiN/GaN interface. With N-passivation, the device shows high ON/OFF current ratio, steep subthreshold slope, low OFF-state leakage current, high breakdown voltage, and improved dynamic ON-resistance. The device reliability under high-electric field stress was also improved as a result.

AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications

The electrical performances of gate-recessed AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated using the damage-free neutral beam etching (NBE) method are demonstrated. The NBE method could eliminate the plasma-induced defects generated by irradiating ultraviolet/VUV photons in the conventional inductively coupled plasma reactive ion etching method. The AlGaN/GaN HEMT device fabricated using the new gate recess process exhibited superior electrical performances, including a maximum drain current density (IDS,max) of 1.54 A/mm, low 1/f noise, a current-gain cutoff frequency (fT) of 153 GHz, a maximum frequency of oscillation (fMAX) of 167 GHz, and a minimum noise figure (NFmin) of 3.28 dB with an associated gain (GAS) of 5.06 dB at 54 GHz. Such superior characteristics confirm the inherent advantages of adopting the damage-free NBE process in fabricating GaN devices for millimeter-wave applications.

Performance Improvements of AlGaN/GaN HEMTs by Strain Modification and Unintentional Carbon Incorporation

An advanced AlGaN/GaN HEMT structure, grown on a sapphire substrate by MOCVD utilizing a high temperature (HT) AlN interlayer (IL) and a multilayer high-low-high temperature (HLH) AlN buffer layer, demonstrates a superior performance both in breakdown voltage (>200 V) and maximum drain current (IDSS = 667 mA/mm). The HT AlN IL produces an additional compressive strain into the above GaN layer. Accordingly, an AlGaN barrier, grown on the more compressive GaN, introduces less tensile strain leading to an improvement in surface morphology (RMS = 0.19 nm in 2 × 2 μm2), a remarkable increase in 2DEG mobility by 46% (μs = 1900 cm2/Vs) and a decrease in densities of defects acting as paths for the leakage current through the AlGaN barrier. A high semi-insulating buffer is achieved by eliminating leakage paths both through the buffer layer and the buffer-substrate interfacial layer. These result from an increase in unintentional carbon introduced by AlN layers, especially by a low temperature AlN layer; which are grown under low pressure (50 Torr). Lastly, the decrease in AlGaN barrier tensile strain and low leakage current in the advanced HEMTs structure using an HT AlN IL and an HLH AlN buffer are promising for an improvement in AlGaN/GaN HEMTs’ reliability.

Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect

We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.

Electrical Analysis and PBTI Reliability of In 0.53 Ga 0.47 As MOSFETs With AlN Passivation Layer and NH 3 Postremote Plasma Treatment

We report a notable improvement in performance, electron transport, and reliability of HfO₂/In_0.53Ga_0.47As nMOSFETs using a plasma-enhanced atomic layer deposition AlN interfacial passivation layer (IPL) and NH₃ postremote plasma treatment (PRPT). The interface state density D_it decreased by approximately one order of magnitude from 6.1×10¹² to 4×10¹¹ cm^-2eV^-1, and the border trap density Nbt also declined ten times from 2.8×10¹⁹ to 2.7×10¹⁸ cm^-3, resulting in the reduction of the accumulation frequency dispersion and eliminate the inversion hump in C-V characteristics, and thus improves the device performances. Furthermore, positive bias temperature instability stress indicates that the sample with the AlN IPL and NH₃ PRPT is more reliable than the sample without any IPL and plasma treatment. During PBT stress, a smaller threshold voltage shift and less transconductance degradation were observed for the sample with the AlN IPL and NH₃ PRPT. In addition, the maximum overdrive voltage for a ten-year operating lifetime increased from 0.19 to 0.41 V.

Improved reliability of GaN HEMTs using N2 plasma surface treatment

In this work, we present a systematic study on AlGaN surface treatment by N2 plasma treatment prior to SiN deposition to enhance the reliability of the AlGaN/GaN MIS-HEMT. N2 plasma treatment can effective remove surface impurities and discharge at the GaN surface, thus improving the SiN/GaN interface quality. With this technique, the GaN MIS-HEMT exhibits excellent reliability after high-gate-bias stress, high-drain-bias stress, and continuously long-term switching.

High V th enhancement mode GaN power devices with high I D, max using hybrid ferroelectric charge trap gate stack

In this work, we demonstrate a new concept for realizing high threshold voltage (V<inf>th</inf>) E-mode GaN power devices with high maximum drain current (I<inf>D, max</inf>). A gate stack ferroelectric blocking film with charge trap layer, achieved a large positive shift of V<inf>th</inf>. The E-mode GaN MIS-HEMTs with high V<inf>th</inf> of 6 V shows I<inf>D, max</inf> 720 mA/mm. The breakdown voltage is above 1100 V.

AlGaN/GaN HEMTs With Damage-Free Neutral Beam Etched Gate Recess for High-Performance Millimeter-Wave Applications (vol 37, pg 1395, 2016)

In the above paper [1] , the first footnote should have included the following information.

Low Leakage Current GaN MIS-HEMT with SiNx Gate Insulator using N2 Plasma Treatment

In this work, an effective N2 plasma treatment for suppressing leakage current in GaN MIS-HEMT has been demonstrated. We observed an important issue of leakage current from the SiNx/GaN interface. To investigate the leakage current mechanisms, we measured the leakage current from all the possible paths in the device structure, such as gate, mesa isolation, and drain leakage. The current−voltage measurement results reveal a severe leakage path at the SiNx/GaN interface after SiNx deposited on the GaN surface without N2 plasma treatment. By using N2 plasma treatment, we succeed in suppressing the leakage current and effectively improve breakdown voltage. A significant performance improvement of GaN MIS-HEMT with very low leakage current has been achieved through the N2 plasma treatment.