Shin Chi Lai

Low Computational Complexity, Low Power, and Low Area Design for the Implementation of Recursive DFT and IDFT Algorithms

A novel recursive algorithm for discrete Fourier transform (DFT) and its inverse transform (IDFT) is proposed in this brief. It was found that the proposed algorithm and its implementation outperformed other existing recursive algorithms. The proposed algorithm was found to 1) reduce multiplication computations by 50.5% using the symmetric identity of coefficients and a resource-sharing technique and register-splitting scheme; 2) decrease read-only memory sizes by 50% compared with conventional algorithms; 3) reduce the number of multipliers implemented by 80% compared with the latest algorithm; and 4) increase data throughput by 100% per transformation. This design is suitable for communication systems and digital radio mondiale (DRM) systems, such as dual-tone multifrequency detection and coded orthogonal frequency-division-multiplexing modulation. The algorithm was designed and fabricated using a 0.18 ¿m 1P6M complementary metal-oxide-semiconductor process. The core area is 397 × 388 ¿m2, including the DFT and IDFT modules. For modern applications (voice over packet and DRM), this processor only consumes 2.96 mW at 25 MHz. Furthermore, it can calculate the 212/165/106/288/256/176/112-point DFTs and IDFTs.

Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC, AAC in DRM, and MP3 Codecs

This paper presents a novel recursive algorithm to compute the modified discrete cosine transform (MDCT) and the inverse MDCT (IMDCT) based on type IV of the discrete cosine transform (DCT-IV) algorithm. The proposed algorithm has the following advantages: In contrast with parallel designs, the input sequence fed by serial in/serial out (SISO) can dynamically be switched with the variable window length. The data throughput per transformation for the MDCT and IMDCT algorithms is four times higher than that of the previous algorithms, and the ROM size can be reduced by 50%-79%. Less memory is required for accessing; thus, it can reduce the chip area in hardware implementation. The chip efficiency is also increased, and the proposed architecture makes a feasible design to integrate several audio standards [i.e., advanced audio coding (AAC)/AAC in digital radio mondiale (DRM/MPEG-1 Audio Layer 3 (MP3)] into one portable media player. The proposed algorithm is designed and fabricated by using 0.18-mum 1P6M complimentary metal-oxide-semiconductor (CMOS) process. The core area is 441 times 437 mum2, including the MDCT, IMDCT, and DCT-IV modules. For modern audio applications, i.e., AAC/AAC in DRM/MP3, this processor only consumes 14.077/3.482/0.3138 mW at 50/12.5/1 MHz. Furthermore, the proposed algorithm can calculate the 2048/1920/256/240/36/12-point MDCT and the 1024/960/128/120/18/6-point IMDCT.

Low-Computation-Cycle, Power-Efficient, and Reconfigurable Design of Recursive DFT for Portable Digital Radio Mondiale Receiver

Low-cost, fast-computational, power-efficient, and reconfigurable design for recursive discrete Fourier transform (RDFT) is proposed in this brief. The proposed method is the first integration that collated both the prime factor algorithm (PFA) and the Chinese reminder theorem (CRT) into a recursive algorithm. Hence, a multicycle RDFT algorithm (PFA + CRT + RDFT) and its hardware implementation are produced and presented here in great detail. Compared with some well-known recursive algorithms, the significant improvements for the proposed algorithm can be summarized as follows: 1) The number of computational cycles of the proposed algorithm can be saved by up to 88.5%; 2) The number of multiplications and additions for the proposed algorithm is dramatically reduced by up to 85.2% and 85.2%, respectively; 3) The amount of coefficient read-only memory for storing the twiddle factors totally takes 694 words fewer than those of other existing RDFT algorithms; 4) The hardware cost of the proposed algorithm only takes four real multipliers and eight real adders. This design is more suitable for digital radio mondiale (DRM) systems, such as coded orthogonal frequency-division-multiplexing modulation. The proposed RDFT algorithm was designed and fabricated using a 0.18-μm 1P6M CMOS process. The core area is 521 × 508 μm2, and this hardware accelerator only consumes 8.44 mW at 25 MHz. Furthermore, the performance index of power for this design is three times discrete Fourier transform (DFT) per energy of previous work. Additionally, it can calculate the 288/256/176/112-point DFTs for a portable DRM receiver.

Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms

Fast algorithms are derived for modified discrete cosine transform (MDCT) and inverse MDCT (IMDCT) in this brief. The proposed algorithms based on type II discrete cosine transform and type II discrete sine transform not only adopt a unified architecture for both MDCT and IMDCT computations but also take only N/8 + 1 computational cycles for each output sequence. Compared with previous IMDCT approaches, the number of preprocessing multiplications of the proposed IMDCT algorithm is reduced by 87.5%. In addition, the coefficient requirements for preprocessing in the proposed IMDCT algorithm can be reduced by 50%, and the number of multiplications for the recursive kernel is greatly decreased by up to 87.5%. The proposed algorithms in terms of hardware costs take two fewer multipliers and six fewer adders than some well-known recursive algorithms. Therefore, the proposed architecture is better suited for various audio codecs.

A Low-Cost, Low-Complexity, and Memory-Free Architecture of Novel Recursive DFT and IDFT Algorithms for DTMF Application

A low-computational complexity and low-cost recursive discrete Fourier transform (RDFT) design using the Chinese remainder theorem is proposed in this brief. The proposed algorithm reduces multiplications by 74% and additions by 73% compared to the latest RDFT algorithms. For computing the 212- and 106-point DFT coefficients, the proposed design can shorten computing cycles by 47% compared with the latest architectures. The hardware resources for the proposed design only require 2 multipliers and 12 adders. The coefficient read-only memory storing the sine and cosine values can be reduced by 100% compared with other recursive algorithms. Therefore, the proposed algorithm is more suitable than other very large scale integration realizations.

Low-Cost and High-Accuracy Design of Fast Recursive MDCT/MDST/IMDCT/IMDST Algorithms and Their Realization

This brief presents a novel low-cost and high-accuracy design for recursive modified discrete cosine transform (MDCT), modified discrete sine transform (MDST), inverse MDCT (IMDCT), and inverse MDST (IMDST) algorithms. The proposed algorithm not only can simultaneously compute MDCT and MDST (or IMDCT and IMDST) coefficients by adopting a compact recursive structure but also can increase the peak signal-to-noise ratio (PSNR) value by selecting the optimal q factor. The PSNR is over 78 dB at least for 256- and 512-point window lengths. Compared with Nikolajevic and Fettweiss algorithm for complexity analysis, the results show that the proposed algorithm greatly reduces 50.21% of multiplications, 24.97% of additions, and 50% of computational cycles for 512-point MDCT and MDST. The FPGA implementation results show that the proposed design can support 7.92 sound-channel encoding and decoding for Dolby AC-3 at a sampling rate of 48 kHz while the clock rate is set to 97 MHz.

A high-precision algorithm for the forward and inverse MDCT using the unified recursive architecture

This paper presents a high-precision algorithm for the forward and inverse MDCT computations using the unified recursive architecture. In this algorithm, the kernel transform of MDCT/IMDCT can share the same architecture because the coefficients for the recursive formula are the same. The preprocessed input samples in the proposed algorithm allow a lower dynamic range than those of other recursive algorithms. Therefore, the proposed algorithm outperforms other MDCT/IMDCT designs in terms of memory storage size, computing cycles and fixed point error if a VLSI implementation of the MDCT/IMDCT is used for MPEG audio coding standards.

A Distortion Cancelation Technique With the Recursive DFT Method for Successive Approximation Analog-to-Digital Converters

This paper proposes a recursive discrete Fourier transform (RDFT) foreground digital calibration method for successive approximation (SAR) analog-to-digital converters (ADCs). This calibration method can lower the harmonic distortion caused by capacitor mismatch and dc offset of comparators to improve the resolution and performance of ADCs. Capacitor mismatch results in a digital-to-analog converter (DAC) capacitor array that is unequal to 2n. RDFT can be adopted to evaluate the real radixes of a DAC capacitor array with a new digital output to compensate for the error caused by capacitor mismatch. Furthermore, the calibration technique can eliminate the dc offset error of a comparator circuit. The proposed novel digital calibration method that utilizes RDFT instead of the traditional fast Fourier transform has the advantages of variable transform length, lower complexity, faster computation, and less hardware cost. The analog block of SAR ADC with RDFT is implemented in the TSMC 0.18-μm standard CMOS process with a 200-kS/s sampling rate to validate the proposed method. Simulation results show that the total harmonic distortion (THD) is 64.97 dB before calibration, whereas a THD of 73.05 dB can be achieved after calibration. In addition, the effective bit numbers are 9.98 and 11.26 b before and after calibration, respectively.

An efficient DCT-IV-based ECG compression algorithm and its hardware accelerator design

This paper presents a new efficient DCT-IV-based ECG compression algorithm with a higher Quality Score (QS) and a better Compressing Ratio (CR). The ECG signals sourced from MIT-BIT arrhythmia database with a sampling rate of 360 Hz are employed to be the test patterns for the evaluating the proposed compression algorithm. The simulation results show that the averages of CR, Percent RMS Difference (PRD), and QS are, respectively, 5.267, 0.187, and 28.223 for all 48 lead-V1 patterns of MIT-BIH database. Compared with Lee et al.s algorithm, the QS value of the proposed method has a great improvement by 25.1%. Additionally, we use DCT-IV to be a unified transform kernel for ECG signal encoding and decoding because the formula of forward DCT-IV is same to its inverse. Also, we realize it to be a compact hardware accelerator with a fewer hardware resources. Therefore, it would be a better choice for realizing the ECG compressor in the future.

An Innovative Fast Algorithm and Structure Design for Analysis and Synthesis Quadrature Mirror Filterbanks on the SBR in DRM

This brief presents a novel fast algorithm derivation and structure design of analysis and synthesis quadrature mirror filterbanks (SQMFs) on the spectral band replication in Digital Radio Mondiale (DRM). After the preprocedure and postprocedure, a Fourier-transform-based computational kernel was required to construct two types of fast algorithms that offered certain advantages. The Proposed-I method employs a modified split-radix fast Fourier transform (FFT) for analysis quadrature mirror filterbank (AQMF) to reduce the number of additions at the last stage of the butterfly and adopts a split-radix FFT to calculate the SQMF coefficients. The Proposed-II method used the compact structure of the variable-length recursive DFT to realize the kernel procedure for the proposed fast AQMF and SQMF algorithms. In addition, a well-known lifting scheme was applied to reduce numerous multiplication and addition calculations. Compared with the original calculations for the long transform length, all multiplication, addition, and coefficient operations for the Proposed-I method (i.e., AQMF + SQMF) had 91.65%, 79.81%, and 97.22% reductions, respectively. However, for the Proposed-II method, the total reductions of multiplication, addition, and coefficient operations were 64.16%, 21.53%, and 97.12%, respectively. Compared with the fast SQMF algorithm by Huang , the Proposed-I method for SQMF reduces 58.33% of the multiplication, 65% of the addition, and 67.19% of the coefficients. Therefore, the proposed fast quadrature mirror filterbank algorithm is a better solution than other approaches for future DRM applications.