Hong Yi Huang

A 1.3 mW low-IF, current-reuse, and current-bleeding RF front-end for the MICS band with sensitivity of -97 dbm

A low-power, low-intermediate frequency (IF) radio frequency (RF) front-end, including low-noise amplifier (LNA) and mixer for the medical implant communications service (MICS) RF band, is presented. The frequencies of LNA and mixer range from 402 MHz to 405 MHz, while the IF of the mixer is 450 KHz. Current-reuse, back-gate coupling, current-bleeding, and feedback circuit design techniques are utilized in the LNA design to achieve 10 dB of gain and the required noise figure (NF) under the low power consumption of 0.94 mW. By contrast, the Gilbert-type mixer generates 20 dB of conversion gain by using current-reuse, back-gate coupling, and current-bleeding techniques. The front-end is operated using a 1.8 V power supply and is capable of achieving a -97 dBm sensitivity using quadrature phase shift keying modulation while consuming 1.3 mW. The proposed front-end is implemented in TSMC 0.18 μm CMOS process with a total area of 1.4 mm × 1.2 mm. The gain enhancement technique has been substantially optimized compared with previous works and measurement results indicate that the front-end obtains the highest figure of merit compared with previous works.

A Distortion Cancelation Technique With the Recursive DFT Method for Successive Approximation Analog-to-Digital Converters

This paper proposes a recursive discrete Fourier transform (RDFT) foreground digital calibration method for successive approximation (SAR) analog-to-digital converters (ADCs). This calibration method can lower the harmonic distortion caused by capacitor mismatch and dc offset of comparators to improve the resolution and performance of ADCs. Capacitor mismatch results in a digital-to-analog converter (DAC) capacitor array that is unequal to 2n. RDFT can be adopted to evaluate the real radixes of a DAC capacitor array with a new digital output to compensate for the error caused by capacitor mismatch. Furthermore, the calibration technique can eliminate the dc offset error of a comparator circuit. The proposed novel digital calibration method that utilizes RDFT instead of the traditional fast Fourier transform has the advantages of variable transform length, lower complexity, faster computation, and less hardware cost. The analog block of SAR ADC with RDFT is implemented in the TSMC 0.18-μm standard CMOS process with a 200-kS/s sampling rate to validate the proposed method. Simulation results show that the total harmonic distortion (THD) is 64.97 dB before calibration, whereas a THD of 73.05 dB can be achieved after calibration. In addition, the effective bit numbers are 9.98 and 11.26 b before and after calibration, respectively.

Analysis and design of a 1.3-mW current-reuse RF front-end for the MICS band

This paper presents a wide-band low-power super-heterodyne RF front-end for the Medical Implant Communications Services (MICS) band. The front-end consists of a low-noise amplifier (LNA), a mixer, buffers, and passive baluns. The proposed circuits feature the techniques of current-reuse, MOSFET back-gate coupling, feedback, and current bleeding to achieve low power under acceptable noise figure (NF) levels for the MICS application. The RF front-end is implemented in 0.18um standard CMOS process with an area of 1.4mm×1.2mm at a supply voltage of 1.8V. Measurement results reveal the capability of a minimum sensitivity of -97dBm, maximum conversion gain of 30dB, and total noise figure (NF) of 11.6 and 13.2 dB while consuming 1.3mW and 2.9mW, respectively.

DAC for positron emission tomography front-end

Positron emission tomography architectures have been traditionally dependent on zero crossing discriminators, external voltage references, or fixed voltage references with restricted voltage steps. This paper presents a digital-to-analog converter (DAC) utilized to set the threshold voltages of Time-of-Flight Positron Emission Tomography (TOF-PET) comparators. The DAC circuit uses a charge redistribution architecture, and all the required building blocks have been fully integrated in a 90 nm CMOS process with an area of 170 × 65 μm2. The power consumption is 324 μW with 1.2-V supply voltage. Using a 10-MHz clock, this DAC achieves an effective number of bits (ENOB) of 8.2.

A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS

A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.

PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing

In this paper, a PVT Insensitive Time to Digital Converter is proposed to provide a stable reference clock signal of a phase-locked loop. The time resolution can be independent on process, voltage, and temperature variations. In order to produce 16-phase signals, eight series of differential delay elements are utilized. Then, interpolated architecture is used to increase the reference frequency such that the time resolution of the time digital converter is improved. Furthermore, implementing a delay element in the oscillator and replica bias circuit can enhance the linearity of the KVCO. Finally, this paper proposes the use of a symmetric time-amplify control circuit, hence, the output pulse width and input cycle time can be synchronized. As the amplification increases the resolution increases, achieving the best resolution of 4.73ps and a maximum detection time of 57.2ns. The test chip is implemented with TSMC 0.18um 1P6M process. The chip area is 0.77×0.32mm2 and the power consumption is 120mW.

A novel clock-pulse-width calibration technique for charge redistribution DACs

This paper presents a novel calibration technique for charge redistribution digital-to-analog converters (DACs). By using the proposed clock-pulse-width calibration, the clock of the DAC is modulated, and the output voltage is effectively modified to enhance the differential-non-linearity (DNL) and integral-non-linearity (INL). By using this method, the measured DNL, and INL have been improved by 61% and 87%, respectively. This calibration is done in few steps, and is aided by a cyclone IV FPGA and an ADC. The DAC has been manufactured in a TSMC 90 nm CMOS process, with a core area of 0.011 mm2. The supply voltage, power consumption, and clock frequency of the IC are 1.2 V, 371 uW, and 8 MHz, respectively.

A 2.5 mW/ch, 50 Mcps, 10-Analog Channel, Adaptively Biased Read-Out Front-End IC With Low Intrinsic Timing Resolution for Single-Photon Time-of-Flight PET Applications With Time-Dependent Noise Analysis in 90 nm CMOS

This paper presents a 10-channel time-of-flight application-specific integrated circuit (ASIC) for positron emission tomography in a 90 nm standard CMOS process. To overcome variations in channel-to-channel timing resolution caused by mismatch and process variations, adaptive biases and a digital-to-analog converter (DAC) are utilized. The main contributions of this work are as follows. First, multistage architectures reduce the total power consumption, and detection bandwidths of analog preamplifiers and comparators are increased to 1 and 1.5 GHz, respectively, relative to those in previous studies. Second, a total intrinsic electronic timing resolution of 9.71 ps root-mean-square (RMS) is achieved (13.88 ps peak and 11.8 ps average of the 10 channels in 5 ASICs). Third, the proposed architecture reduces variations in channel-to-channel timing resolution to 2.6 bits (equivalent to 4.17 ps RMS) by calibrating analog comparator threshold levels. A 181.5 ps full-width-at-half-maximum timing resolution is measured with an avalanche photo diode and a laser setup. The power consumption is 2.5 mW using 0.5 and 1.2 V power supplies. The proposed ASIC is implemented in a 90 nm TSMC CMOS process with a total area of 3.3 mm

A digitally self-calibration method with recursive DFT algorithm for 12-bit SAR ADC realization

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All digital phase-locked loop using active inductor oscillator and novel locking algorithm

2.7 mm.